參數(shù)資料
型號: CY7C1371AV25-66AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 512K X 36 ZBT SRAM, 10 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù): 16/26頁
文件大?。?/td> 333K
代理商: CY7C1371AV25-66AC
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
23
Switching Waveforms (continued)
ADV/LD
CLK
ADDRESS
CE
1a
Data
In/Out
tCYC
tCH tCL
tALS
tALH
RA1
tAH
tAS
tCES tCEH
tCDV
Q1
= DON’T CARE
= UNDEFINED
The combination of WE & BWSx(x=a, b, c, d) define a write cycle (see Write Cycle Description table).
Out
B
e
gi
n
R
e
ad
Bu
rs
tR
e
a
d
tCLZ
tDOH
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Device
originally deselected
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
WA2
Q1+1
Out
Q1+2
Out
Q1+3
Out
RA3
tCLZ
tCHZ
D2+1
In
D2+2
In
D2+3
In
D2
In
tCDV
Q3
Out
tDS
tDH
Bu
rs
tR
e
a
d
B
u
rs
tR
ead
B
egi
n
W
ri
te
Bu
rs
tWr
it
e
Bu
rs
tWr
it
e
Bu
rs
tW
ri
te
B
e
gi
n
R
ead
B
u
rs
tR
ead
Bu
rs
tR
e
a
d
Burst Sequences
BWSx
tWES
tWEH
WE
tWS tWH
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWSx input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
Out
Q3+1
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