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參數(shù)資料
| 型號： | CY7C1371AV25-66AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 10 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 333K |
| 代理商： | CY7C1371AV25-66AC |
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CY7C1371AV25
CY7C1373AV25
PRELIMINARY
6
Pin Definitions (119 BGA)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5, C6, G4, R2, R6,
T2, T3, T5, T6
P4, N4, A2, A3, A5,
A6, B3, B5, C2, C3,
C5 C6, R2, R6, G4,
T3, T4, T5
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the 266,144 ad-
dress locations. Sampled at the rising edge of the CLK.
L5, G3
L5, G5, G3, L3
BWSa
BWSb
BWSc
BWSd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct writes to the SRAM. Sampled on the rising
edge of CLK. BWSa controls DQa and DPa, BWSb con-
trols DQb and DPb, BWSc controls DQc and DPc, BWSd
controls DQd and DPd.
H4
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
B4
ADV/LD
Input-
Synchronous
Advance/Local Input used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected,
ADV/LD should be driven LOW in order to load a new
address.
K4
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only rec-
ognized if CEN is active LOW.
E4
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK.
F4
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchro-
nous logic block inside the device to control the direction
of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the
first clock when emerging from a deselected state and
when the device has been deselected.
M4
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW
the clock signal is recognized by the SRAM. When deas-
serted HIGH the clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
(a)P7, N6, L6, K7,
H6, G7, F6, E7
(b)N1, M2, L1, K2,
H1, G2, E2, D1
(a)P7, N7, N6, M6,
L7, L6, K7, K6
(b)D7, E7, E6, F6,
G7, G6, H7, H6
(c)D1, E1, E2, F2,
G1, G2, H1, H2
(d)P1, N1, N2, M2,
L1, L2, K1, K2
DQa
DQb
DQc
DQd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by A[x:0] during the previous
clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE
is asserted LOW, the pins can behave as outputs. When
HIGH, DQa–DQd are placed in a three-state condition.
The outputs are automatically three-stated during the
data portion of a write sequence, during the first clock
when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
D6, P2
P6, D6, D2, P2
DPa
DPb
DPc
DPd
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these
signals are identical to DQa–DQd. During write sequenc-
es, DPa is controlled by BWSa, DPb is controlled by
BWSb, DPc is controlled by BWSc, and DPd is controlled
by BWSd.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1371B100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371B-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1371B117AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371BV25-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371C-100AC | 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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