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參數(shù)資料
| 型號： | CY7C1371AV25-66AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 10 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 24/26頁 |
| 文件大?。?/td> | 333K |
| 代理商： | CY7C1371AV25-66AC |
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CY7C1371AV25
CY7C1373AV25
PRELIMINARY
7
Functional Overview
The CY7C1371AV25/CY7C1373AV25 is a Synchronous
Flow-Through Burst NoBL SRAM designed specifically to
eliminate wait states during Write-Read transitions. All syn-
chronous inputs pass through input registers controlled by the
rising edge of the clock. The clock signal is qualified with the
Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Accesses can be initiated by asserting Chip Enable(s) (CE1,
CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising
edge of the clock. If Clock Enable (CEN) is active LOW and
ADV/LD is asserted LOW, the address presented to the device
will be latched. The access can either be a Read or Write op-
eration, depending on the status of the Write Enable (WE).
Byte Write Selects can be used to conduct byte write opera-
tions.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry
Synchronous Chip Enable (CE1, CE2, and CE3 on the TQFP,
CE1 on the BGA) and an asynchronous Output Enable (OE)
simplify depth expansion. All operations (Reads, Writes, and
Deselects) are pipelined. ADV/LD should be driven LOW once
the device has been deselected in order to load a new address
for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
R3
MODE
Input
Strap Pin
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW
selects the linear burst order. MODE should not change
states during operation. When left floating MODE will
default HIGH, to an interleaved burst order.
C4, J2, J4, J6, R4
VDD
Power Supply
Power supply inputs to the core of the device.
A1, A7, F1, F7, J1,
J7, M1, M7, U1, U7
A1, A7, F1, F7, J1
J7, M1, M7, U1, U7
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
D3, D5, E3, E5, F3,
F5, H3, H5, K3, K5,
M3, M5, N3, N5, P3,
P5, R5
D3, D5, E3, E5, F3,
F5, H3, H5, K3, K5,
M3, M5, N3, N5,
P3, P5, R5
VSS
Ground
Ground for the device. Should be connected to ground
of the system.
J3, J5
VSS(1)
These pins have to be tied to a voltage level < VIL. They
need not be tied to VSS.
U5
TDO
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK.
U3
TDI
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK.
U2
TMS
Test Mode Se-
lect
Synchronous
This pin controls the Test Access Port state machine.
Sampled on the rising edge of TCK.
U4
TCK
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK.
A4, T6, T1
A4, T4, T2
16M,
32M
64M
-
No connects. Reserved for address expansion.
B1, B2, B7, C1, C7,
D2, D4, D7, E1, E6,
F2, G1, G5, G6, H2,
H7, J3, J5, K1, K6,
L2, L3, L4, M6, N2,
N7, P1, P6, R1, R7,
T7
B2, B7, C7, D4, J3,
J5, L4, R1, R7, T1,
T7
NC
-
No connects.
U6
DNU
-
Do not use pin.
Pin Definitions (119 BGA) (continued)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1371B100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371B-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1371B117AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371BV25-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371C-100AC | 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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