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參數(shù)資料
| 型號(hào)： | CY7C1371AV25-66AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 10 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 333K |
| 代理商： | CY7C1371AV25-66AC |
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CY7C1371AV25
CY7C1373AV25
PRELIMINARY
11
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1371AV25/CY7C1373AV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are in-
ternally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the oper-
ation of the device.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data In (TDI)
The TDI pin is used to serially input information into the regis-
ters and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruc-
tion that is loaded into the TAP instruction register. For infor-
mation on loading the instruction register, see the TAP Con-
troller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (See TAP Controller State dia-
gram). The output changes on the falling edge of TCK. TDO is
connected to the Least Significant Bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block dia-
gram. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as de-
scribed in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long regis-
ter, and the x18 configuration has a yy-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Defi-
nitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit in-
struction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RE-
SERVED and should not be used. The other five instructions
are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller can-
not be used to load address, data, or control signals into the
SRAM and cannot preload the Input or Output buffers. The
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參數(shù)描述 |
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| CY7C1371B100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371B-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CY7C1371C-100AC | 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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