參數(shù)資料
型號(hào): CY7C1371AV25-66AC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 512K X 36 ZBT SRAM, 10 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù): 26/26頁
文件大?。?/td> 333K
代理商: CY7C1371AV25-66AC
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
9
Notes:
1.
X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables. CE = 0 stands for ALL Chip Enables are active.
2.
Write is defined by WE and BWSx. BWSx = Valid signifies that the desired byte write selects are asserted. See Write Cycle Description table for details.
3.
The DQ and DP pins are controlled by the current cycle and the OE signal.
4.
CEN=1 inserts wait states.
5.
Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6.
OE assumed LOW.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation
Address
used
CE
CEN
ADV/
LD
WE
BWSx
CLK
Comments
Deselected
External
1
0
X
L-H
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
L-H
Clock ignored, all operations sus-
pended.
Begin Read
External
0
1
X
L-H
Address latched.
Begin Write
External
0
Valid
L-H
Address latched, data presented
two valid clocks later.
Burst READ
Operation
Internal
X
0
1
X
L-H
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst WRITE
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWSa,b,c,d/BWSa,b.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
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