參數(shù)資料
型號(hào)： CY7C1371AV25-66AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 512K X 36 ZBT SRAM, 10 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 25/26頁(yè)
文件大?。?/td> 333K
代理商： CY7C1371AV25-66AC
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
8
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read ac-
cess is in progress and allows the requested data to propagate
to the output buffers. The data is available within 6.5 ns
(133-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1371AV25/CY7C1373AV25 has an on-chip burst
counter that allows the user the ability to supply a single ad-
dress and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented suf-
ficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) Chip En-
able(s) asserted active, and (3) the write signal WE is asserted
LOW. The address presented is loaded into the Address Reg-
ister. The write signals are latched into the Control Logic block.
The data lines are automatically three-stated regardless of the
state of the OE input signal. This allows the external logic to
present the data on DQ and DP.
On the next clock rise the data presented to DQ and DP (or a
subset for byte write operations, see Write Cycle Description
table for details) inputs is latched into the device and the write
is complete. Additional accesses (Read/Write/Deselect) can
be initiated on this cycle.
The data written during the Write operation is controlled by
Byte
Write
Select
signals.
The
CY7C1371AV25/
CY7C1373AV25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write En-
able input (WE) with the selected Byte Write Select input will
selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A synchro-
nous self-timed write mechanism has been provided to simpli-
fy the write operations. Byte write capability has been included
in order to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.
Because the CY7C1371AV25/CY7C1373AV25 are common
I/O devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DP inputs. Doing
so will three-state the output drivers. As a safety precaution,
DQ and DP are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1371AV25/CY7C1373AV25 has an on-chip burst
counter that allows the user the ability to supply a single ad-
dress and conduct up to four Write operations without reas-
serting the address inputs. ADV/LD must be driven LOW in
order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is in-
cremented. The correct BWSa,b,c,d/BWSa,b inputs must be
driven in each cycle of the burst write in order to write the
correct bytes of data.
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參數(shù)描述
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CY7C1371C-100AC 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán)
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