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參數(shù)資料
| 型號(hào)： | CY7C1371AV25-66AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 10 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 14/26頁 |
| 文件大?。?/td> | 333K |
| 代理商： | CY7C1371AV25-66AC |
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CY7C1371AV25
CY7C1373AV25
PRELIMINARY
21
Switching Characteristics Over the Operating Range[16]
117
100
83
66
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Clock
tCYC
Clock Cycle Time
8.5
10.0
12.0
15.0
ns
FMAX
Maximum Operating Frequency
117
100
83
66
MHz
tCH
Clock HIGH
3.0
ns
tCL
Clock LOW
3.0
ns
Output Times
tCDV
Data Output Valid After CLK Rise
7.5
8.5
9.0
10.0
ns
tEOV
OE LOW to Output Valid[14, 19]
3.5
4.0
ns
tDOH
Data Output Hold After CLK Rise
1.5
ns
tCHZ
Clock to High-Z[17, 18, 19]
1.5
5.0
1.5
5.0
1.5
5.0
1.5
5.0
ns
tCLZ
Clock to Low-Z[17, 18, 19]
3
ns
tEOHZ
OE HIGH to Output High-Z[17, 18, 19]
4.0
ns
tEOLZ
OE LOW to Output Low-Z[17, 18, 19]
0
ns
Set-up Times
tAS
Address Set-Up Before CLK Rise
2.0
ns
tDS
Data Input Set-Up Before CLK Rise
2.0
ns
tCENS
CEN Set-Up Before CLK Rise
2.0
ns
tWES
WE, BWSx Set-Up Before CLK Rise
2.0
ns
tALS
ADV/LD Set-Up Before CLK Rise
2.0
ns
tCES
Chip Select Set-Up
2.0
ns
Hold Times
tAH
Address Hold After CLK Rise
0.5
ns
tDH
Data Input Hold After CLK Rise
0.5
ns
tCENH
CEN Hold After CLK Rise
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
ns
Shaded areas contain advance information.
Notes:
16. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
17. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
18. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1371B100AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371B-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C1371B117AC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371BV25-100AC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371C-100AC | 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
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