參數(shù)資料
型號(hào)： CY7C1371AV25-66AC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 512K X 36 ZBT SRAM, 10 ns, PQFP100
封裝： 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁(yè)數(shù)： 22/26頁(yè)
文件大小： 333K
代理商： CY7C1371AV25-66AC
CY7C1371AV25
CY7C1373AV25
PRELIMINARY
5
74, 24
51, 80, 1, 30
DPa
DPb
DPc
DPd
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these sig-
nals are identical to DQ[31:0]. During write sequences,
DPa is controlled by BWSa, DPb is controlled by BWSb,
DPc is controlled by BWSc, and DPd is controlled by
BWSd.
31
MODE
Input
Strap pin
Mode Input. Selects the burst order of the device. Tied
HIGH selects the interleaved burst order. Pulled LOW se-
lects the linear burst order. MODE should not change
states during operation. When left floating MODE will de-
fault HIGH, to an interleaved burst order.
15, 41, 65, 66, 91
VDD
Power Supply
Power supply inputs to the core of the device.
4, 11, 20, 27, 54,
61, 70, 77
4, 11, 20, 27, 54,
61, 70, 77
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
5, 10, 14, 17, 21,
26, 40, 55, 60, 67,
71, 76, 90
5, 10, 14,17, 21, 26,
40, 55, 60, 67, 71,
76, 90
VSS
Ground
Ground for the device. Should be connected to ground of
the system.
64, 84
1-3, 6, 7, 25, 28-30,
51-53, 64, 75, 78,
79
NC
-
No connects. Reserved for address expansion to 512K
depths.
38, 39, 42, 43
DNU
-
Do Not Use pins. These pins should be left floating.
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Location
x36 Pin Location
Name
I/O Type
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C1371B100AC 制造商:Cypress Semiconductor 功能描述:
CY7C1371B-100AC 制造商:Rochester Electronics LLC 功能描述:- Bulk
CY7C1371B117AC 制造商:Cypress Semiconductor 功能描述:
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CY7C1371C-100AC 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類(lèi)型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤(pán)
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