- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄295376 > CY7C1413BV18-250BZXI (CYPRESS SEMICONDUCTOR CORP) 2M X 18 QDR SRAM, 0.45 ns, PBGA165 PDF資料下載
參數(shù)資料
| 型號： | CY7C1413BV18-250BZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 2M X 18 QDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, M0-216, FBGA-165 |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 726K |
| 代理商： | CY7C1413BV18-250BZXI |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
36-Mbit QDR-II SRAM 4-Word
Burst Architecture
CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Cypress Semiconductor Corporation
198 Champion Court
San Jose
, CA 95134-1709
408-943-2600
Document Number: 001-07037 Rev. *D
Revised June 16, 2008
Features
■ Separate independent read and write data ports
Supports concurrent transactions
■ 300 MHz clock for high bandwidth
■ 4-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 600 MHz) at 300 MHz
■ Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR-II operates with 1.5 cycle read latency when DLL is
enabled
■ Operates as a QDR-I device with 1 cycle read latency in DLL
off mode
■ Available in x 8, x 9, x 18, and x 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 (±0.1V); IO VDDQ = 1.4V to VDD
■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1411BV18 – 4M x 8
CY7C1426BV18 – 4M x 9
CY7C1413BV18 – 2M x 18
CY7C1415BV18 – 1M x 36
Functional Description
The CY7C1411BV18, CY7C1426BV18, CY7C1413BV18, and
CY7C1415BV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture
consists of two separate ports to access the memory array. The
read port has dedicated data outputs to support the read opera-
tions and the write port has dedicated data inputs to support the
write operations. QDR-II architecture has separate data inputs
and data outputs to completely eliminate the need to
“turn-around” the data bus required with common IO devices.
Access to each port is through a common address bus.
Addresses for read and write addresses are latched on alternate
rising edges of the input (K) clock. Accesses to the QDR-II read
and write ports are completely independent of one another. To
maximize data throughput, read and write ports are equipped
with DDR interfaces. Each address location is associated with
four
8-bit
words
(CY7C1411BV18),
9-bit
words
(CY7C1426BV18), 18-bit words (CY7C1413BV18), or 36-bit
words (CY7C1415BV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds.”
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on chip
synchronous self-timed write circuitry.
Selection Guide
Description
300 MHz
278 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
300
278
250
200
167
MHz
Maximum Operating Current
x8
885
815
745
620
535
mA
x9
900
830
760
620
535
x18
940
865
790
655
565
x36
1040
950
870
715
615
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C145-35JCR | 8K X 9 DUAL-PORT SRAM, 35 ns, PQCC68 |
| CY7C1472BV25-250BZXI | 4M X 18 ZBT SRAM, 3 ns, PBGA165 |
| CY7C164-15PC | 16K x 4 Static RAM |
| CY7C164-25PC | 16K x 4 Static RAM |
| CY7C164-15VC | 16K x 4 Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1413JV18-200BZXI | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 QDR-II BURST 4 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1413JV18-250BZI | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 QDR-II Burst 4 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1413JV18-250BZXC | 功能描述:靜態(tài)隨機存取存儲器 36-Mbit QDR 靜態(tài)隨機存取存儲器 4-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1413JV18-250BZXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1413JV18-300BZC | 功能描述:靜態(tài)隨機存取存儲器 2Mx18 QDR II Burst 4 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。