參數(shù)資料
型號： CY7C1413BV18-250BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 2M X 18 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, M0-216, FBGA-165
文件頁數(shù)： 27/30頁
文件大?。?/td> 726K
代理商： CY7C1413BV18-250BZXI
CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Document Number: 001-07037 Rev. *D
Page 6 of 30
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
CY7C1411BV18
D
[7:0]
CY7C1426BV18
D
[8:0]
CY7C1413BV18
D
[17:0]
CY7C1415BV18
D
[35:0]
WPS
Input-
Synchronous
Write Port Select
Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
NWS0,
NWS1,
Input-
Synchronous
Nibble Write Select 0, 1
Active LOW (CY7C1411BV18 Only). Sampled on the rising edge of the K
and K clocks when write operations are active. Used to select which nibble is written into the device during
the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3
Active LOW. Sampled on the rising edge of the K and K clocks when
write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1426BV18
BWS
0 controls D[8:0]
CY7C1413BV18
BWS
0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1415BV18
BWS
0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4M x 8 (4 arrays each of 1M x 8) for CY7C1411BV18, 4M x 9 (4 arrays each of 1M x 9) for CY7C1426BV18,
2M x 18 (4 arrays each of 512K x 18) for CY7C1413BV18 and 1M x 36 (4 arrays each of 256K x 36) for
CY7C1415BV18. Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1411BV18 and CY7C1426BV18, 19 address inputs for CY7C1413BV18 and 18 address inputs for
CY7C1415BV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
data is driven out on the rising edge of the C and C clocks during read operations or K and K, when in
single clock mode. On deselecting the read port, Q[x:0] are automatically tri-stated.
CY7C1411BV18
Q
[7:0]
CY7C1426BV18
Q
[8:0]
CY7C1413BV18
Q
[17:0]
CY7C1415BV18
Q
[35:0]
RPS
Input-
Synchronous
Read Port Select
Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of four sequential transfers.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
相關PDF資料
PDF描述
CY7C145-35JCR 8K X 9 DUAL-PORT SRAM, 35 ns, PQCC68
CY7C1472BV25-250BZXI 4M X 18 ZBT SRAM, 3 ns, PBGA165
CY7C164-15PC 16K x 4 Static RAM
CY7C164-25PC 16K x 4 Static RAM
CY7C164-15VC 16K x 4 Static RAM
相關代理商/技術參數(shù)
參數(shù)描述
CY7C1413JV18-200BZXI 功能描述:靜態(tài)隨機存取存儲器 2Mx18 QDR-II BURST 4 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413JV18-250BZI 功能描述:靜態(tài)隨機存取存儲器 2Mx18 QDR-II Burst 4 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413JV18-250BZXC 功能描述:靜態(tài)隨機存取存儲器 36-Mbit QDR 靜態(tài)隨機存取存儲器 4-Word Burst RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
CY7C1413JV18-250BZXI 制造商:Cypress Semiconductor 功能描述:
CY7C1413JV18-300BZC 功能描述:靜態(tài)隨機存取存儲器 2Mx18 QDR II Burst 4 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*