參數(shù)資料
型號(hào): CY7C1413BV18-250BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類(lèi): SRAM
英文描述: 2M X 18 QDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, M0-216, FBGA-165
文件頁(yè)數(shù): 11/30頁(yè)
文件大小: 726K
代理商: CY7C1413BV18-250BZXI
CY7C1411BV18, CY7C1426BV18
CY7C1413BV18, CY7C1415BV18
Document Number: 001-07037 Rev. *D
Page 19 of 30
Power Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
Apply VDD before VDDQ.
Apply VDDQ before VREF or at the same time as VREF.
Drive DOFF HIGH.
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
DLL Constraints
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Figure 3. Power Up Waveforms
> 1024 Stable clock
Start Normal
Operation
DOFF
Stable (< +/- 0.1V DC per 50ns )
Fix High (or tie to VDDQ)
K
DDQ
DD
V
/
DDQ
DD
V
/
Clock Start (Clock Starts after
Stable)
DDQ
DD
V
/
~ ~
~~
Unstable Clock
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