參數(shù)資料
型號(hào)： CY7C1515AV18-250BZXI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 2M X 36 QDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù)： 2/31頁(yè)
文件大小： 774K
代理商： CY7C1515AV18-250BZXI
CY7C1511AV18, CY7C1526AV18
CY7C1513AV18, CY7C1515AV18
Document Number: 001-06985 Rev. *D
Page 10 of 31
Application Example
Figure 1 shows four QDR-II used in an application.
Figure 1. Application Example
Truth Table
The truth table for CY7C1511AV18, CY7C1526AV18, CY7C1513AV18, and CY7C1515AV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
DQ
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L-H
H [8]
L [9] D(A) at K(t + 1)
↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Read Cycle:
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
L-H
L [9]
XQ(A) at C(t + 1)
↑ Q(A + 1) at C(t + 2)↑ Q(A + 2) at C(t + 2)↑ Q(A + 3) at C(t + 3)↑
NOP: No Operation
L-H
H
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
D = X
Q = High-Z
Standby: Clock Stopped
Stopped
X
Previous State
R = 250
ohms
Vt
R
R = 250
ohms
Vt
R
Vt = Vddq/2
R = 50
ohms
R
CC#
D
A
SRAM #4
R
P
S
#
W
P
S
#
B
W
S
#
K
ZQ
CQ/CQ#
Q
K#
CC#
D
A
K
SRAM #1
R
P
S
#
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
K#
BUS
MASTER
(CPU
or
ASIC)
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
CLKIN/CLKIN#
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
↑represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
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