參數(shù)資料
型號(hào): CY7C1515AV18-250BZXI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 2M X 36 QDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165
文件頁(yè)數(shù): 3/31頁(yè)
文件大小: 774K
代理商: CY7C1515AV18-250BZXI
CY7C1511AV18, CY7C1526AV18
CY7C1513AV18, CY7C1515AV18
Document Number: 001-06985 Rev. *D
Page 11 of 31
Write Cycle Descriptions
The write cycle description table for CY7C1511AV18 and CY7C1513AV18 follows. [2, 10]
BWS0/
NWS0
BWS1/
NWS1
K
Comments
L
L–H
During the data portion of a write sequence
:
CY7C1511AV18
both nibbles (D
[7:0]) are written into the device,
CY7C1513AV18
both bytes (D
[17:0]) are written into the device.
L
L-H During the data portion of a write sequence
:
CY7C1511AV18
both nibbles (D
[7:0]) are written into the device,
CY7C1513AV18
both bytes (D
[17:0]) are written into the device.
L
H
L–H
During the data portion of a write sequence
:
CY7C1511AV18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1513AV18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L–H During the data portion of a write sequence
:
CY7C1511AV18
only the lower nibble (D
[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1513AV18
only the lower byte (D
[8:0]) is written into the device, D[17:9] remains unaltered.
H
L
L–H
During the data portion of a write sequence
:
CY7C1511AV18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1513AV18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L–H During the data portion of a write sequence
:
CY7C1511AV18
only the upper nibble (D
[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1513AV18
only the upper byte (D
[17:9]) is written into the device, D[8:0] remains unaltered.
H
L–H
No data is written into the devices during this portion of a write operation.
H
L–H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1526AV18 follows. [2, 10]
BWS0
K
Comments
L
L–H
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
L–H
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
No data is written into the device during this portion of a write operation.
H
L–H
No data is written into the device during this portion of a write operation.
Note
10. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
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