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參數(shù)資料
| 型號： | DM9601E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB Ethernet MAC Controller with Intergrated 10/100 PHY |
| 中文描述： | USB以太網(wǎng)MAC控制器與集成10/100網(wǎng)卡芯片 |
| 文件頁數(shù)： | 19/58頁 |
| 文件大?。?/td> | 603K |
| 代理商： | DM9601E |
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DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9601-DS-F01
June 22, 2002
19
Key to Default
In the register description that follows, the default column
takes the form:
<Reset Value>, <Access Type>
Where
：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C = Read
and Clear
RW/C1=Read/Write and Cleared by write 1
WO = Write only
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read access.
10.1 Network Control Register (00H)
Bit
7
Name
EXT_PHY
Default
0,RW
Description
Select External PHY When Set
When clear select Internal PHY. This bit will not be affected after a software reset
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clear all wakeup
event status.
This bit will not be affected after a software reset.
Reserved
Force Collision Mode, used for testing.
Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
Loopback Mode
Bit 2 1
0 0 normal
0 1 MAC internal loopback
1 0 internal PHY digital loopback
1 1 internal PHY analog loopback
Software reset and auto clear after 10us
6
WAKEEN
0,RW
5
4
3
RESERVED
FCOL
FDX
LBK
0,RO
0,RW
0,RW
00,RW
2:1
0
RST
0,RW
10.2 Network Status Register (01H)
Bit
7
Name
SPEED
Default
X,RO
Description
Media speed 0:100Mbps 1:10Mbps, when internal PHY is used. This bit is no
meaning when LINKST=0
Link status 0:link failed 1:link OK, when internal PHY is used
Wakeup Event Status
Clears by read or write 1. This bit will not be affected after a software reset
TX FIFO Full
When there are two packets in TX SRAM, TX FIFO FULL will be set
TX Packet 2 Complete Status
Clears by read or write 1.Transmit completion of packet index 2
TX Packet 1 Complete Status
Clears by read or write 1. Transmit completion of packet index 1
RX FIFO Overflow
RX Packet Ready, there are one or more packets in RX FIFO
6
5
LINKST
WAKEST
X,RO
0,RW/C1
4
TXFULL
0,RO
3
TX2END
0,RW/C1
2
TX1END
0,RW/C1
1
0
RXOV
RXRDY
0,RO
0,RO
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DM9601J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Retriggerable One Shot |
| DM9601N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DM9601W | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Retriggerable One Shot |
| DM9601W/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| DM9602 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual Retriggerable, Resettable One Shots |
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