
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Final
Version: DM9601-DS-F01
June 22, 2002
25
10.19 General purpose Register ( 1FH )
Bit
7
6:1
Name
RESERVED
GEPIO6-1
Default
0,RO
0,RW
Description
Reserved
General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is output to pin GEPIO6-1
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit be read is reflected from correspondent pins of GEPIIO6-1
The GEPIOs are mapped to pins GEPIO6 to GEPIO1 respectively
General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is output to pin GEPIO0
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit be read is reflected from pin GEPIO0
GEPIO0 default output 1 to POWER_DOWN internal PHY. Driver need to clear this
POWER_DOWN signal by write “0” when it wants PHY active. If other device need,
it also can refer this signal. This default value can be programmed by EEPROM.
Please refer EEPROM description
0
GEPIO0
1,RW
10.20 TX SRAM Write Pointer Address Register (20H~21H)
Bit
7:0
7:0
Name
TWPAH
TWPAL
Default
00H,RO
00H.RO
Description
TX SRAM write pointer address high byte (21H)
TX SRAM write pointer address low byte (20H)
10.21 TX SRAM Read Pointer Address Register (22H~23H)
Bit
7:0
7:0
Name
TRPAH
TRPAL
Default
00H,RO
00H.RO
Description
TX SRAM read pointer address high byte (23H)
TX SRAM read pointer address low byte (22H)
10.22 RX SRAM Write Pointer Address Register (24H~25H)
Bit
7:0
7:0
Name
RWPAH
RWPAL
Default
0CH,RO
04H.RO
Description
RX SRAM write pointer address high byte (25H)
RX SRAM write pointer address low byte (24H)
10.23 RX SRAM Read Pointer Address Register (26H~27H)
Bit
7:0
7:0
Name
RRPAH
RRPAL
Default
0CH,RO
00H.RO
Description
RX SRAM read pointer address high byte (27H)
RX SRAM read pointer address low byte (26H)