DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
32
Final
Version: DM9601-DS-F01
June 22, 2002
11.5 Auto-negotiation Advertisement Register(ANAR) – 04
This register contains the advertised abilities of this DM9601 device as they will be transmitted to its link partner
during Auto-negotiation.
Bit
Bit Name
Default
Description
4.15
NP
0,RO/P
Next Page Indication
0 = No next page available
1 = Next page available
The PHY has no next page, so this bit is permanently set to 0
Acknowledge
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
The PHY's auto-negotiation state machine will automatically
control this bit in the outgoing FLP bursts and set it at the
appropriate time during the auto-negotiation process. Software
should not attempt to write to this bit
Remote Fault
1 = Local device senses a fault condition
0 = No fault detected
Reserved
Write as 0, ignore on read
Flow Control Support
1 = Controller chip supports flow control ability
0 = Controller chip doesn’t support flow control ability
100BASE-T4 Support
1 = 100BASE-T4 is supported by the local device
0 = 100BASE-T4 is not supported
The PHY does not support 100BASE-T4 so this bit is permanently
set to 0
100BASE-TX Full Duplex Support
1 = 100BASE-TX full duplex is supported by the local device
0 = 100BASE-TX full duplex is not supported
100BASE-TX Support
1 = 100BASE-TX is supported by the local device
0 = 100BASE-TX is not supported
10BASE-T Full Duplex Support
1 = 10BASE-T full duplex is supported by the local device
0 = 10BASE-T full duplex is not supported
10BASE-T Support
1 = 10BASE-T is supported by the local device
0 = 10BASE-T is not supported
Protocol Selection Bits
These bits contain the binary encoded protocol selector supported
by this node
<00001> indicates that this device supports IEEE 802.3 CSMA/CD
4.14
ACK
0,RO
4.13
RF
0, RW
4.12-4.11
RESERVED
X, RW
4.10
FCS
0, RW
4.9
T4
0, RO/P
4.8
TX_FDX
1, RW
4.7
TX_HDX
1, RW
4.6
10_FDX
1, RW
4.5
10_HDX
1, RW
4.4-4.0
Selector
<00001>, RW