參數(shù)資料
型號: DM9601E
廠商: Electronic Theatre Controls, Inc.
英文描述: USB Ethernet MAC Controller with Intergrated 10/100 PHY
中文描述: USB以太網(wǎng)MAC控制器與集成10/100網(wǎng)卡芯片
文件頁數(shù): 35/58頁
文件大小: 603K
代理商: DM9601E
DM9601
USB to Ethernet MAC Controller with Integrated 10/100 PHY
Preliminary
Version: DM9601-DS-P01
June 22, 2001
35
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes
Reserved
Write as 0, ignore on read
Reserved
Write as 0, ignore on read
Reduced Power Down Control Enable
This bit is used to enable automatic reduced power down
0 : Disable automatic reduced power down
1 : Enable automatic reduced power down
Reset State Machine
When writes 1 to this bit, all state machines of PHY will be reset.
This bit is self-clear after reset is completed
MF Preamble Suppression Control
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
Sleep Mode
Writing a 1 to this bit will cause PHY entering the Sleep mode and
power down all circuit except oscillator and clock generator circuit.
When waking up from Sleep mode (write this bit to 0), the
configuration will go back to the state before sleep; but the state
machine will be reset
Remote Loopout Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
16.6
RESERVED
0, RO
16.5
RESERVED
0, RO
16.4
RPDCTR-EN
1, RW
16.3
SMRST
0, RW
16.2
MFPSC
0, RW
16.1
SLEEP
0, RW
16.0
RLOUT
0, RW
11.9 DAVICOM Specified Configuration and Status Register (DSCSR) - 17
Bit
Bit Name
Default
Description
17.15
100FDX
1, RO
100M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M full duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
100M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 100M half duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode
10M Full Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
If this bit is 1, it means the operation 1 mode is a 10M Full Duplex
mode. The software can read bit[15:12] to see which mode is
selected after auto-negotiation. This bit is invalid when it is not in the
auto-negotiation mode.
10M Half Duplex Operation Mode
After auto-negotiation is completed, results will be written to this bit.
17.14
100HDX
1, RO
17.13
10FDX
1, RO
17.12
10HDX
1, RO
相關(guān)PDF資料
PDF描述
DM9602 Dual Retriggerable, Resettable One Shots
DM9602N Dual Retriggerable, Resettable One Shots
DM96L02 Dual Retriggerable Resettable Monostable Multivibrator
DM96L02N Dual Retriggerable Resettable Monostable Multivibrator
DM9701F Gigabit Ethernet PHY Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9601J 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Retriggerable One Shot
DM9601N 制造商:Rochester Electronics LLC 功能描述:- Bulk
DM9601W 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Retriggerable One Shot
DM9601W/883 制造商:Rochester Electronics LLC 功能描述:- Bulk
DM9602 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Dual Retriggerable, Resettable One Shots