參數(shù)資料
型號： DS2154LNA2+
廠商： Maxim Integrated Products
文件頁數(shù)： 105/124頁
文件大?。?/td> 0K
描述： IC TXRX E1 5V 100-LQFP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
類型： 收發(fā)器
驅動器/接收器數(shù)： 1/1
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
81 of 124
15.1.
Receive Clock and Data Recovery
The DS21354/DS21554 contain a digital clock recovery system. See Figure 2-1 and Figure 15-1 for more
details. The device couples to the receive-E1-shielded twisted pair or coax via a 1:1 transformer. See
Table 15-3 for transformer details. The 2.048MHz clock attached at the MCLK pin is internally
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16-times oversampler, which is used to recover the clock
and data. This oversampling technique offers outstanding jitter tolerance (Figure 15-3).
Normally, the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI/HDB3
waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,
a receive carrier loss (RCL) condition occurs, and the RCLKO is sourced from the clock applied at the
MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLKO output
can exhibit slightly shorter high cycles of the clock, which is due to the highly oversampled digital clock
recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case in most applications),
the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see the Receive AC
Timing Characteristics for more details.
15.2.
Transmit Waveshaping and Line Driving
The DS21354/DS21554 use a set of laser-trimmed delay lines along with a precision digital-to-analog
converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the
ITU G.703 specifications (see Figure 15-5).
The user selects which waveform is to be generated by properly programming the L2/L1/L0 bits in the
Line Interface Control Register (LICR). The DS21354/DS21554 can set up in a number of various
configurations depending on the application. See tables below and Figure 15-5.
Table 15-1. Line Build-Out Select in LICR for the DS21554
L2
L1
L0
APPLICATION
TRANSFORMER
RETURN LOSS
(dB)*
RT (
W)
**
0
75
W normal
1:1.15 step-up
N.M.
0
1
120
W normal
1:1.15 step-up
N.M.
0
1
0
75
W with protection resistors
1:1.15 step-up
N.M.
8.2
0
1
120
W with protection resistors
1:1.15 step-up
N.M.
8.2
1
0
75
W with high return loss
1:1.15 step-up
21
27
1
0
75
W with high return loss
1:1.36 step-up
21
18
1
0
120
W with high return loss
1:1.36 step-up
21
27
* N.M. = Not Meaningful (return loss value too low for significance).
** Refer to Application Note 324 for details on E1 line interface design.
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