參數(shù)資料
型號: DS2154LNA2+
廠商: Maxim Integrated Products
文件頁數(shù): 124/124頁
文件大小: 0K
描述: IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
99 of 124
Figure 17-1. IBO Basic Configuration Using Four SCTs
17.1.
Channel Interleave
In channel interleave mode data is output to the PCM data-out bus one channel at a time from each of the
connected SCTs until all channels of frame n from all each SCT has been place on the bus. This mode can
be used even when the connected SCTs are operating asynchronous to each other. The elastic stores will
manage slip conditions. See Figure 18-11 and Figure 18-5 for details.
17.2.
Frame Interleave
In frame-interleave mode, data is output to the PCM data-out bus one frame at a time from each of the
connected SCTs. This mode is used only when all connected SCTs are synchronous. In this mode, slip
conditions are not allowed. See Figure 18-2 and Figure 18-6 for details.
RSYSCLK
TSYSCLK
RSYNC
TSSYNC
CI
CO
RSIG
TSIG
TSER
RSER
RSYSCLK
TSYSCLK
CI
CO
RSIG
TSIG
TSER
RSER
RSYSCLK
TSYSCLK
CI
CO
RSIG
TSIG
TSER
RSER
RSYSCLK
TSYSCLK
CI
CO
RSIG
TSIG
TSER
RSER
MASTER
SCT
SLAVE #1
SLAVE #2
SALVE #3
8.192MHz System Clock In
System 8KHz Frame Sync In
PCM Data Out
PCM Data In
PCM Signaling Out
PCM Signaling In
RSYNC
TSSYNC
RSYNC
TSSYNC
RSYNC
TSSYNC
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