參數(shù)資料
型號(hào)： DS2154LNA2+
廠商： Maxim Integrated Products
文件頁數(shù)： 64/124頁
文件大?。?/td> 0K
描述： IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 90
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
44 of 124
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)
(MSB)
(LSB)
TESF
TESE
JALT
RESF
RESE
CRCRC
FASRC
CASRC
SYMBOL
POSITION
NAME AND DESCRIPTION
TESF
RIR.7
Transmit-Side Elastic Store Full. Set when the transmit-side elastic
store buffer fills and a frame is deleted.
TESE
RIR.6
Transmit-Side Elastic Store Empty. Set when the transmit-side elastic
store buffer empties and a frame is repeated.
JALT
RIR.5
Jitter Attenuator Limit Trip. Set when the jitter attenuator FIFO reaches
to within 4–bits of its limit; useful for debugging jitter attenuation
operation.
RESF
RIR.4
Receive-Side Elastic Store Full. Set when the receive side elastic store
buffer fills and a frame is deleted.
RESE
RIR.3
Receive-Side Elastic Store Empty. Set when the receive side elastic store
buffer empties and a frame is repeated.
CRCRC
RIR.2
CRC Resync Criteria Met. Set when 915/1000 codewords are received
in error.
FASRC
RIR.1
FAS Resync Criteria Met Event (FASRC). Set when three consecutive
FAS words are received in error. Note: During a CRC resync the FAS
synchronizer is brought online to verify the FAS alignment. If during this
process a FAS emulator exists, the FAS synchronizer may temporarily
align to the emulator. The FASRC will go active indicating a search for a
valid FAS has been activated.
CASRC
RIR.0
CAS Resync Criteria Met. Set when two consecutive CAS MF
alignment words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address = 1E Hex)
(MSB)
(LSB)
CSC5
CSC4
CSC3
CSC2
CSC0
FASSA
CASSA
CRC4SA
SYMBOL
POSITION
NAME AND DESCRIPTION
CSC5
SSR.7
CRC4 Sync Counter Bit 5. MSB of the 6-bit counter.
CSC4
SSR.6
CRC4 Sync Counter Bit 4.
CSC3
SSR.5
CRC4 Sync Counter Bit 3.
CSC2
SSR.4
CRC4 Sync Counter Bit 2.
CSC0
SSR.3
CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. The next to LSB is
not accessible.
FASSA
SSR.2
FAS Sync Active. Set while the synchronizer is searching for alignment
at the FAS level.
CASSA
SSR.1
CAS MF Sync Active. Set while the synchronizer is searching for the
CAS MF alignment word.
CRC4SA
SSR.0
CRC4 MF Sync Active. Set while the synchronizer is searching for the
CRC4 MF alignment word.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2154LNA2+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2154LND2 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2154LND2+ 制造商:Maxim Integrated Products 功能描述:ENHANCED E1 SCT LQFP REVD2 IND LF - Rail/Tube
DS2155 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
DS2155_06 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:T1/E1/J1 Single-Chip Transceiver
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