參數(shù)資料
型號： DS2154LNA2+
廠商： Maxim Integrated Products
文件頁數(shù)： 85/124頁
文件大?。?/td> 0K
描述： IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
類型： 收發(fā)器
驅動器/接收器數(shù)： 1/1
規(guī)程： E1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
63 of 124
11.
CLOCK BLOCKING REGISTERS
The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel
blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,
respectively. (The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either
high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD
controller in ISDN–PRI applications.
When the appropriate bits are set to one, the RCHBLK and TCHBLK pin will be held high during the
entire corresponding channel time. See the timing in Section 18 for an example. The TCBRs have
alternate mode of use. Via the CCR3.6 bit, the user has the option to use the TCBRs to determine on a
channel by channel basis, which signaling bits are to be inserted via the TSRs (the corresponding bit in
the TCBRs = 1) and which are to be sourced from the TSER or TSIG pins (the corresponding bit in the
TCBR = 0). See the timing in Section 18.2 for an example.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING REGISTERS
(Address = 2B to 2E Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
RCBR1 (2B)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
RCBR2 (2C)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
RCBR3 (2D)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
RCBR4 (2E)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1 to
CH32
RCBR1.0 to
RCBR4.7
Receive Channel Blocking Control Bits.
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING REGISTERS
(Address = 22 to 25 Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TCBR1 (22)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TCBR2 (23)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TCBR3 (24)
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
TCBR4 (25)
SYMBOL
POSITION
NAME AND DESCRIPTION
CH1 to
CH32
TCBR1.0 to
TCBR4.7
Transmit Channel Blocking Control Bits.
0 = force the TCHBLK pin to remain low during this channel time
1 = force the TCHBLK pin high during this channel time
Note: If CCR3.6 = 1, then a zero in the TCBRs implies that signaling data is to be sourced from
TSER (or TSIG if CCR3.2 = 1), and a one implies that signaling data for that channel is to be
sourced from the Transmit Signaling (TS) registers. In this mode, the voice-channel numbering
scheme (CH1 to CH30) is used. See the following definition.
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