3.1.3. Parallel Control Port Pins Signal Name: INT Signal Description: Int" />
參數(shù)資料
型號(hào): DS2154LNA2+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 38/124頁(yè)
文件大?。?/td> 0K
描述: IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
20 of 124
3.1.3.
Parallel Control Port Pins
Signal Name:
INT
Signal Description:
Interrupt
Signal Type:
Output
Active-low, open-drain output that flags host controller during conditions and change of conditions
defined in the Status Registers 1 and 2 and the HDLC Status Register.
Signal Name:
FMS
Signal Description:
Framer Mode Select
Signal Type:
Input
Selects the DS2154 mode when high or the DS21354/DS21554 mode when low. If high, the
JTRST is
internally pulled low. If low,
JTRST has normal JTAG functionality. This pin has a 10k
W pullup resistor.
Signal Name:
TEST
Signal Description:
Tri-State Control
Signal Type:
Input
Set high to tri-state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board-level testing.
Signal Name:
MUX
Signal Description:
Bus Operation
Signal Type:
Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
AD0 to AD7
Signal Description:
Data Bus [D0 to D7] or Address/Data Bus
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as an 8-bit multiplexed address/data bus.
Signal Name:
A0 to A6
Signal Description:
Address Bus
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.
Signal Name:
BTS
Signal Description:
Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the
RD (DS), ALE (AS), and WR (R/W) pins. If BTS = 1, then these pins assume the function
listed in parentheses ().
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