參數(shù)資料
型號: DS2154LNA2+
廠商: Maxim Integrated Products
文件頁數(shù): 4/124頁
文件大?。?/td> 0K
描述: IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
101 of 124
Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)
Figure 18-4. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)
RSER
CHANNEL 23/31
CHANNEL 24/32
CHANNEL 1/2
RCHCLK
RCHBLK
RSYSCLK
RSYNC
2
3
RSYNC
1
RMSYNC
LSB
F
MSB
LSB
4
NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1
LINK IS (MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED
TO ON1).
NOTE 2: RSYNC IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 3: RSYNC IN THE INPUT MODE (RCR1.5 = 1).
NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.
RSER
CHANNEL 1
RCHCLK
RCHBLK
RSYSCLK
RSYNC
CHANNEL 31
CHANNEL 32
1
3
RSYNC
2
RMSYNC
RSIG
CHANNEL 31
CHANNEL 32
C
D
AB
CHANNEL 1
LSB MSB
C
D
B
A
Note 4
NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0).
NOTE 2: RSYNC IS IN THE INPUT MODE (RCR1.5 = 1).
NOTE 3: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
NOTE 4: RSIG NORMALLY CONTAINS THE CAS MULTIFRAME ALIGNMENT NIBBLE (0000) IN CHANNEL 1.
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