參數(shù)資料
型號: DS2154LNA2+
廠商: Maxim Integrated Products
文件頁數(shù): 16/124頁
文件大?。?/td> 0K
描述: IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
112 of 124
20.
AC TIMING PARAMETERS AND DIAGRAMS
20.1.
Multiplexed Bus AC Characteristics
AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (MUX = 1)
(VDD = 3.3V
±5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V ±5%, TA = 0°C to +70°C for DS21554L;
VDD = 3.3V
±5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V ±5%, TA = -40°C to +85°C for DS21554LN.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Cycle Time
tCYC
200
ns
Pulse Width, DS Low or
RD High
PWEL
100
ns
Pulse Width, DS High or
RD Low
PWEH
100
ns
Input Rise/Fall Yimes
tR, tF
20
ns
R/
W Hold Time
tRWH
10
ns
R/
W Setup Time before DS High
tRWS
50
ns
CS Setup Time before DS, WR, or RD
Active
tCS
20
ns
CS Hold Time
tCH
0
ns
Read Data Hold Time
tDHR
10
50
ns
Write Data Hold Time
tDHW
0
ns
Muxed Address Valid to AS or ALE Fall
tASL
15
ns
Muxed Address Hold Time
tAHL
10
ns
Delay time DS,
WR, or RD to AS or ALE
Rise
tASD
20
ns
Pulse Width AS or ALE High
PWASH
30
ns
Delay time, AS or ALE to DS,
WR, or RD
tASED
10
ns
Output Data Delay Time from DS or
RD
tDDR
20
80
ns
Data Setup Time
tDSW
50
ns
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