參數(shù)資料
型號(hào): DS2154LNA2+
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 36/124頁(yè)
文件大?。?/td> 0K
描述: IC TXRX E1 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 1/1
規(guī)程: E1
電源電壓: 4.75 V ~ 5.25 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤(pán)
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
19 of 124
Signal Name:
8MCLK
Signal Description:
8MHz Clock
Signal Type:
Output
An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
RPOSO
Signal Description:
Receive Positive Data Input
Signal Type:
Output
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied
to RPOSI.
Signal Name:
RNEGO
Signal Description:
Receive Negative Data Input
Signal Type:
Output
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally
tied to RNEGI.
Signal Name:
RCLKO
Signal Description:
Receive Clock Output
Signal Type:
Output
Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI.
Signal Name:
RPOSI
Signal Description:
Receive Positive Data Input
Signal Type:
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the
LIUC pin high.
Signal Name:
RNEGI
Signal Description:
Receive Negative Data Input
Signal Type:
Input
Sampled on the falling edge of RCLKI for data to be clocked through the receive-side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the
LIUC pin high.
Signal Name:
RCLKI
Signal Description:
Receive Clock Input
Signal Type:
Input
Clock used to clock data through the receive-side framer. This pin is normally tied to RCLKO. Can be
internally connected to RCLKO by tying the LIUC pin high.
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