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參數(shù)資料
| 型號： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 35/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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DS3105
18
7.
Functional Description
7.1
Overview
The DS3105 has five input clocks and two output clocks. There are two separate DPLLs in the device: the high-
performance T0 DPLL and the simpler the T4 DPLL. The T0 DPLL can generate output clocks; the T4 DPLL can
be used to monitor inputs for frequency and phase. See Figure 3-1.
Three of the input clock pins are single-ended and can accept clock signals from 2kHz to 125MHz. The other two
are differential inputs that can accept clock signals up to 156.25MHz. The differential inputs can be configured to
accept differential LVDS or LVPECL signals or single-ended CMOS/TTL signals.
Each input clock can be monitored continually for activity, and each can be marked unavailable or given a priority
number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special
modes, the highest priority valid input is automatically selected as the reference for the T0 DPLL. SRFAIL is set or
cleared based on activity and/or frequency of the selected input.
Both the T0 DPLL and the T4 DPLL can directly lock to many common telecom and datacom frequencies,
including, but not limited to, 8kHz, DS1, E1, 10MHz, 19.44MHz, and 38.88MHz as well as Ethernet frequencies
including 25MHz, 62.5MHz, 125MHz, and 156.25MHz. The DPLLs can also lock to multiples of the standard direct-
lock frequencies including 8kHz.
The T0 DPLL is the high-performance path with all the features needed for synchronizing a line card to dual
redundant system timing cards. The T4 DPLL can be used to monitor input clock signals but it cannot drive any
output clocks. The T4 APLL is always connected to the T0 DPLL to provide low-jitter output frequencies from the
T0 DPLL. There is also a dedicated low-jitter APLL output that operates at 312.5MHz for 10G Ethernet
applications.
Using the optional PLL bypass, the T4 selected reference, after any frequency division, can be directly output on
either of the OC3 or OC6 output clock pins.
Both DPLLs have these features:
Automatic reference selection based on input activity and priority
Manual reference selection/forcing
Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor
Ability to lock to several common telecom and Ethernet frequencies plus multiples of any standard
direct lock frequency
Six bandwidth selections from 18Hz to 400Hz
The T0 DPLL has these additional features not available in the T4 DPLL:
A full state machine for automatic transitions among free-run, locked, and holdover states
Optional manual reference switching mode
Nonrevertive reference switching mode
Phase build-out for reference switching (“hitless”)
Output vs. input phase offset control
Noise rejection circuitry for low-frequency references
Output phase alignment to input frame-sync signal
Instant digital one-second averaging and free-run holdover modes
Frequency conversion between input and output using digital frequency synthesis
The T4 DPLL has an additional feature not available in the T0 DPLL:
Optional mode to measure the phase difference between two input clocks
Typically, the internal state machine controls the T0 DPLL, but manual control by system software is also available.
The T4 DPLL has a simpler state machine that software cannot directly control. In either DPLL, however, software
can override the DPLL logic using manual reference selection.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3105LN+ | 功能描述:計時器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3106 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC |
| DS3106A10SL3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S(621) | 制造商:Amphenol Corporation 功能描述: |
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