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參數(shù)資料
| 型號(hào)： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 65/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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DS3105
45
Table 7-19. External Frame-Sync Mode and Source
T0 DPLL
LOCKED
1
EFSEN
SOURCE
AEFSEN
SYNCSRC
SELREF
FRAME-SYNC
MODE
FRAME-SYNC
SOURCE
0
X
XXXX
2
X
XXX
XXXX
Disabled
Internal
3
1
0
XXXX
X
XXX
XXXX
Disabled
Internal
1
<>11XX
0
XXX
XXXX
SYNC1 Manual
SYNC1
1
<>11XX
1
XXX
=FSCR3:
SOURCE
SYNC1 Auto
SYNC1
<>FSCR3:
SOURCE
Internal
1
11XX
X
4
0XX
IC3 or IC5
SYNC123
(Auto
4)
SYNC1
IC4 or IC6
SYNC2
1X0
IC3
SYNC1
IC4
SYNC2
1X1
IC5
SYNC1
IC6
SYNC2
XXX
IC9
SYNC3
all other cases
Internal
Note 1:
That is, when OPSTATE:T0STATE = 100.
Note 2:
X = Don’t care.
Note 3:
None of the SYNCn pins is used. The internal 2kHz alignment generators free-run at their existing alignment. See Section 7.9.5.
Note 4:
When SOURCE=11XX, selection and enable of SYNCn pins are automatic regardless of the setting of AEFSEN. In this mode the
AEFSEN bit is retasked to specify whether or not MCR3:EFSEN is automatically cleared when the T0 DPLL’s selected reference
changes.
7.9.2 Sampling
By default the external frame-sync signal on the enabled SYNCn pin is first sampled on the rising edge of the
selected reference. This gives the most margin, given that the external frame-sync signal is falling-edge aligned
with the selected reference since both come from the same timing card. The expected timing of the SYNCn signal
with respect to the sampling clock can be adjusted from 0.5 cycles early to 1 cycle late using the
FSCR2:PHASEn[1:0] field.
7.9.3 Resampling
The SYNCn signal is then resampled by an internal clock derived from the T0 DPLL. The resampling resolution is a
function of the frequency of the selected reference and FSCR2:OCN. When OCN = 0, the resampling resolution is
6.48MHz, which gives the most sampling margin and also aligns all clocks at 6.48MHz and multiples thereof. When
OCN = 1, if the selected reference is 19.44MHz, the resampling resolution is 19.44MHz. If the selected reference is
38.88MHz, the resampling resolution is 38.88MHz. The selected reference must be either 19.44MHz or 38.88MHz
when OCN = 1.
7.9.4 Qualification
The SYNCn signal is qualified when it has consistent phase and correct frequency. Specifically, it is qualified when
its significant edge has been found at exact 2kHz boundaries (when resampled as previously described) for 64
cycles in a row. It is disqualified when one significant edge is not found at the 2kHz boundary.
7.9.5 Output Clock Alignment
When the T0 DPLL is locked, external frame sync is enabled, and the SYNCn signal is qualified, the SYNCn signal
can be used to falling-edge align the T0 DPLL derived output clocks. Output clocks FSYNC and MFSYNC share a
2kHz alignment generator, while the rest of the T0 DPLL-derived output clocks share a second 2kHz alignment
generator. When external frame sync is not enabled or the SYNCn signal is not qualified, these 2Hz alignment
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相關(guān)代理商/技術(shù)參數(shù) |
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| DS3105LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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