- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1994 > DS3105LN+ (Maxim Integrated Products)IC TIMING LINE CARD 64-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 53/124頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)當(dāng)前第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)
DS3105
34
Table 7-5. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode
LOCKING MODE
FOR T4
FORCED
REFERENCE
LOCKING
MODE FOR T0
SELECTED
REFERENCE
LOCKING
MODE FOR
COPY OF T0
SELECTED
REFERENCE
FREQUENCY OF THE
T4 FORCED
REFERENCE FOR
T4MT0 PHASE
MEASUREMENT
FREQUENCY OF THE
T0 SELECTED
REFERENCE FOR
T4MT0 PHASE
MEASUREMENT
LOCK8K or
DIVN(8K)
DIRECT
LOCK8K
8kHz
LOCK8K or
DIVN(8K)
LOCK8K
8kHz
LOCK8K or
DIVN(8K)
DIVN (8K)
DIVN
8kHz
LOCK8K or
DIVN(8K)
DIVN (not 8K)
DIRECT
8kHz
DIVN (not 8K)
Any
DIRECT
Same as the T4 forced
reference input
frequency
Same as the T0 selected
reference input
frequency
(1)
DIRECT
Any
DIRECT
Same as the T4 forced
reference input
frequency
Same as the T0 selected
reference input
frequency
(1)
Note 1: In this case, the T0 select reference must be the same frequency as the T4 selected reference.
Note 2: If the T4 selected reference frequency is 8kHz and the T0 selected reference is a different frequency, the two references can be
compared by configuring the T4 forced reference for 8kHz and LOCK8K mode. This forces the copy of the T0 selected reference to be divided
down to 8kHz using either LOCK8K or DIVN mode.
Note 3: DIVN(8K) means that the FREQ field is set to 8kHz, DIVN(not 8K) means the FREQ field is not set to 8kHz.
7.7.11 Input Jitter Tolerance
The device is compliant with the jitter tolerance requirements of the standards listed in Table 1-1. When using the
±360°/±180° PFD, jitter can be tolerated up to the point of eye closure. Either LOCK8K mode (see Section 7.4.2.2)
or the multicycle phase detector (see Section 7.7.5) should be used for high jitter tolerance.
7.7.12 Jitter Transfer
The transfer of jitter from the selected reference to the output clocks has a programmable transfer function that is
determined by the DPLL bandwidth. (See Section 7.7.3.) In the T0 DPLL, the 3dB corner frequency of the jitter
transfer function can be set to any of 7 positions from 18Hz to 400Hz. In the T4 DPLL the 3dB corner frequency of
the jitter transfer function can be set to various values from 18Hz to 70Hz.
7.7.13 Output Jitter and Wander
Several factors contribute to jitter and wander on the output clocks, including:
Jitter and wander amplitude on the selected reference (while in the locked state)
The jitter transfer characteristic of the device (while in the locked state)
The jitter and wander on the local oscillator clock signal (especially wander while in the holdover
state)
The DPLL in the device has programmable bandwidth (see Section 7.7.3). With respect to jitter, the DPLL behaves
as a lowpass filter with a programmable pole. The bandwidth of the DPLL is normally set low enough to strongly
attenuate jitter.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS3106LN+ | IC TIMING LINE CARD 64-LQFP |
| DS3231MZ+ | IC RTC I2C 8SOIC |
| DS3231SN#T&R | IC RTC W/TCXO 16-SOIC |
| DS3232MZ+ | IC RTC W/SRAM I2C 8SOIC |
| DS3232SN#T&R | IC RTC W/TCXO 20-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3105LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3106 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC |
| DS3106A10SL3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S(621) | 制造商:Amphenol Corporation 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。