參數(shù)資料
型號(hào): DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 47/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 160
類型: 定時(shí)卡 IC,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
29
7.7.1.6.1 Automatic Holdover
For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or
averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current
frequency 50ms to 100ms before entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2, and
FREQ3 registers when MCR11:T4T0 = 0). The FREQ field is the DPLL’s integral path and, therefore, is an average
frequency with a rate of change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not
used in order to minimize the effect of recent phase disturbances on the holdover frequency.
In averaged mode (AVG = 1 in HOCR3 and FRUNHO = 1 in MCR3), the holdover frequency is set to an internally
averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a
one-second period. The T0 DPLL indicates that it has acquired a valid holdover value by setting the HORDY status
bit in VALSR2 (real-time status) and MSR4 (latched status). If the T0 DPLL must enter holdover before the
one-second average is available, an instantaneous value 50ms to 100ms old from the integral path is used instead.
7.7.1.6.2 Free-Run Holdover
For free-run holdover (FRUNHO = 1 in MCR3), the output frequency accuracy is generated with the accuracy of
the external oscillator frequency. The actual frequency is the frequency of the external oscillator plus the value of
the MCLK offset specified in the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). When
MCR3.FRUNHO is set the HOCR3:AVG bit is ignored.
7.7.1.7 Mini-Holdover
When the selected reference fails, the fast activity monitor (Section 7.5.3) isolates the T0 DPLL from the reference
within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the
DPLL enters a temporary mini-holdover mode, with a frequency equal to an instantaneous value 50ms to 100 ms
old from the integral path of the loop filter. Mini-holdover lasts until the selected reference becomes active or the
state machine enters the holdover state. If the free-run holdover mode is set (FRUNHO = 1 in MCR3), the mini-
holdover frequency accuracy is exactly the same as the external oscillator accuracy plus the offset set by the
MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3).
7.7.2 T4 DPLL State Machine
The T4 DPLL state machine is simpler than the T0 DPLL state machine. The T4 DPLL does not generate any
output clock signals but it can be used to measure phase between two inputs and it can lock to an input to measure
the frequency and possibly stability of the input.
7.7.3 Bandwidth
The bandwidth of the T4 DPLL is configured in the T4BW register to be 18Hz to 70Hz.
The bandwidth of the T0 DPLL is configured in the T0ABW and T0LBW registers for various values from 18Hz to
400Hz. The AUTOBW bit in the MCR9 register controls automatic bandwidth selection. When AUTOBW = 1, the
T0 DPLL uses the T0ABW bandwidth during acquisition (not phase-locked) and the T0LBW bandwidth when
phase-locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition
and when phase-locked.
When LIMINT = 1 in the MCR9 register, the DPLL’s integral path is limited (i.e., frozen) when the DPLL reaches
minimum or maximum frequency. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in.
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