參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 91/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 定時卡 IC,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
69
Register Name:
MCR2
Register Description:
Master Configuration Register 2
Register Address:
33h
Bit #
7
6
5
4
3
2
1
0
Name
T0FORCE[3:0]
Default
0
1
Bits 3 to 0: T0 DPLL Force Selected Reference (T0FORCE[3:0]). This field provides a way to force a specified
input clock to be the selected reference for the T0 DPLL. Internally this is accomplished by forcing the clock to have
the highest priority (as specified in PTAB1:REF1). In revertive mode (MCR3:REVERT = 1) the forced clock
automatically becomes the selected reference (as specified in PTAB1:SELREF) as well. In nonrevertive mode the
forced clock only becomes the selected reference when the existing selected reference is invalidated or made
unavailable for selection.
When a reference is forced, the activity monitor for that input and the T0 DPLL’s loss-of-lock timeout logic all
continue to operate and affect the relevant ISR, VALSR, and MSR register bits. However, when the reference is
declared invalid the T0 DPLL is not allowed to switch to another input clock. The T0 DPLL continues to respond to
the fast activity monitor, transitioning to mini-holdover in response to short-term events and to full holdover in
response to longer events. See Section 7.6.3.
0000 = Automatic source selection (normal operation)
0001 = {unused value, undefined}
0010 = {unused value, undefined}
0011 = Force to IC3
0100 = Force to IC4
0101 = Force to IC5
0110 = Force to IC6
0111 = {unused value}
1000 = {unused value, undefined}
1001 = Force to IC9
1010–1110 = {unused values}
1111 = Automatic source selection (normal operation)
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