參數(shù)資料
型號(hào)： DS3105LN+
廠商： Maxim Integrated Products
文件頁數(shù)： 77/124頁
文件大小： 0K
描述： IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 160
類型： 定時(shí)卡 IC，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum，電信
輸入： CMOS，LVDS，LVPECL，TTL
輸出： CMOS，LVDS，LVPECL，TTL
電路數(shù)： 1
比率 - 輸入:輸出： 5:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 312.5MHz
電源電壓： 1.62 V ~ 1.98 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
DS3105
56
Register Name:
MSR1
Register Description:
Master Status Register 1
Register Address:
05h
Bit #
7
6
5
4
3
2
1
0
Name
—
IC6
IC5
IC4
IC3
—
Default
1
0
1
Bits 5 to 2: Input Clock Status Change (IC[6:3]). Each of these latched status bits is set to 1 when the
corresponding VALSR1 status bit changes state (set or cleared). Each bit is cleared when written with a 1 and not
set again until the VALSR1 bit changes state again. When one of these latched status bits is set, it can cause an
interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the IER1 register. See
Section 7.5 for input clock validation/invalidation criteria.
Register Name:
MSR2
Register Description:
Master Status Register 2
Register Address:
06h
Bit #
7
6
5
4
3
2
1
0
Name
STATE
SRFAIL
—
IC9
Default
0
1
Bit 7: T0 DPLL State Change (STATE). This latched status bit is set to 1 when the operating state of the T0 DPLL
changes. STATE is cleared when written with a 1 and not set again until the operating state changes again. When
STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the
IER2 register. The current operating state can be read from the T0STATE field of the OPSTATE register. See
Section 7.7.1.
Bit 6: Selected Reference Failed (SRFAIL). This latched status bit is set to 1 when the selected reference to the
T0 DPLL fails, (i.e., no clock edges in two UI). SRFAIL is cleared when written with a 1. When SRFAIL is set it can
cause an interrupt request on the INTREQ pin if the SRFAIL interrupt enable bit is set in the IER2 register. SRFAIL
is not set in free-run mode or holdover mode. See Section 7.5.3.
Bit 0: Input Clock Status Change (IC9). This latched status bit is set to 1 when the corresponding VALSR status
bit changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until the VALSR2 bit
changes state again. When this latched status bit is set it can cause an interrupt request on the INTREQ pin if the
corresponding interrupt enable bit is set in the IER2 register. See Section 7.5 for input clock validation/invalidation
criteria.
Register Name:
FREQ3
Register Description:
Frequency Register 3
Register Address:
07h
Bit #
7
6
5
4
3
2
1
0
Name
—
FREQ[18:16]
Default
0
Bits 2 to 0: Current DPLL Frequency (FREQ[18:16]). See the FREQ1 register description.
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