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參數(shù)資料
| 型號： | DS3105LN+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 44/124頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING LINE CARD 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | 定時(shí)卡 IC，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum，電信 |
| 輸入： | CMOS，LVDS，LVPECL，TTL |
| 輸出： | CMOS，LVDS，LVPECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 5:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 1.62 V ~ 1.98 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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DS3105
26
Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations,
temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers.
DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock
(204.8MHz) is multiplied up from the 12.800MHz local oscillator clock applied to the REFCLK pin. This master
clock is then digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1ns pk-
pk.
The analog PLLs filter the jitter from the DPLLs, reducing the 1ns pk-pk jitter to less than 0.5ns pk-pk and 60ps
RMS, typical, measured broadband (10Hz to 1GHz).
The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input
frequency, pull-in/hold-in range, input-to-output phase offset, phase build-out, and more. No knowledge of loop
equations or gain parameters is required to configure and operate the device. No external components are
required for the DPLLs or the APLLs except the high-quality local oscillator connected to the REFCLK pin.
The T0 DPLL has a full free-run/locked/holdover state machine and full programmability. The secondary T4 DPLL
can be used to measure frequency and phase of inputs but cannot supply output clock signals.
7.7.1 T0 DPLL State Machine
The T0 DPLL has three main timing modes: locked, holdover, and free-run. The control state machine for the T0
DPLL has states for each timing mode as well as three temporary states: prelocked, prelocked 2, and loss-of-lock.
The state transition diagram is shown in Figure 7-2. Descriptions of each state are given in the paragraphs below.
During normal operation the state machine controls state transitions. When necessary, however, the state can be
forced using the T0STATE field of the MCR1 register.
Whenever the T0 DPLL changes state, the STATE bit in MSR2 is set, which can cause an interrupt request if
enabled. The current T0 DPLL state can be read from the T0STATE field of the OPSTATE register.
7.7.1.1 Free-Run State
Free-run mode is the reset default state. In free-run all output clocks are derived from the 12.800 MHz local
oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local
oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock,
which can be calibrated using the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). The state
machine transitions from free-run to the prelocked state when at least one input clock is valid.
7.7.1.2 Prelocked State
The prelocked state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the
selected reference. If phase lock (see Section 7.7.6) is achieved for 2 seconds during this period, the state
machine transitions to locked mode.
If the DPLL fails to lock to the selected reference within the phase-lock timeout period specified by PHLKTO, a
phase-lock alarm is raised (corresponding LOCK bit set in the ISR register), invalidating the input (ICn bit goes low
in VALSR registers). If another input clock is valid, the state machine re-enters the prelocked state and tries to lock
to the alternate input clock. If no other input clocks are valid for two seconds, the state machine transitions back to
the free-run state.
In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock
timeout period, the state machine re-enters the prelocked state and tries to lock the higher priority input.
If a phase-lock timeout period longer than 100 seconds is required for locking, the PHLKTO register must be
configured accordingly.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3105LN+ | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Line Card Timing IC RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| DS3106 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Line Card Timing IC |
| DS3106A10SL3S(621) | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S | 制造商:Amphenol Corporation 功能描述: |
| DS3106A14S2S(621) | 制造商:Amphenol Corporation 功能描述: |
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