參數(shù)資料
型號: DS3105LN+
廠商: Maxim Integrated Products
文件頁數(shù): 55/124頁
文件大?。?/td> 0K
描述: IC TIMING LINE CARD 64-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 160
類型: 定時卡 IC,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum,電信
輸入: CMOS,LVDS,LVPECL,TTL
輸出: CMOS,LVDS,LVPECL,TTL
電路數(shù): 1
比率 - 輸入:輸出: 5:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 1.62 V ~ 1.98 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
DS3105
36
7.8.2.2 Output DFS and APLL Details
See Figure 7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS
blocks, and three APLL DFS blocks. The T0 APLL, the T0 APLL2, and the T4 APLL (and their output dividers) get
their frequency references from three associated APLL DFS blocks. All the output DFS blocks are connected to the
T0 DPLL.
The 2K8K DFS and FSYNC DFS blocks generate both 2kHz and 8kHz signals, which have about 1ns pk-pk jitter.
The FSYNC (8kHz) and MFSYNC(2 kHz) signals come from the FSYNC DFS block, which is always connected to
the T0 DPLL when not in independent mode (FSCR2:INDEP = 1). In independent mode they will be frequency
locked, but not phase aligned with the OC3 and OC6 outputs. The 2kHz and 8 kHz signals that can be output on
OC3 or OC6 always come from the 2K8K DFS, which is always connected to the T0 DPLL.
The DIG1 DFS can generate an N x DS1 or N x E1 signal with about 1ns pk-pk jitter. The DIG2 DFS can generate
an N x DS1, N x E1, 6.312MHz, 10MHz, or N x 19.44MHz clock with approximately 1ns pk-pk jitter. The frequency
of the DIG1 clock is configured by the DIG1SS bit in MCR6 and the DIG1F[1:0] field in MCR7. The frequency of the
DIG2 clock is configured by the DIG2AF and DIG2SS bits in MCR6 and the DIG2F[1:0] field in MCR7. DIG1 and
DIG2 can be independently configured for any of the frequencies shown in Table 7-7 and Table 7-8, respectively.
The APLL DFS blocks and their associated output APLLs and output dividers can generate many different
frequencies. The APLL DFS blocks are always connected to the T0 DPLL. The T0 APLL frequencies that can be
generated are listed in Table 7-10. The T0 APLL2 frequency is always 312.500MHz. The T4 APLL frequencies that
can be generated are listed in Table 7-12. The output frequencies that can be generated from the APLL circuits are
listed in Table 7-9.
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