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參數(shù)資料
| 型號(hào)： | DSM2150F5V-12T6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存）的ADI公司的DSP（3.3V電源） |
| 文件頁數(shù)： | 24/73頁 |
| 文件大小： | 1067K |
| 代理商： | DSM2150F5V-12T6 |
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DSM2150F5V
24/73
PLDs
The PLDs bring programmable logic to the device.
After specifying the logic for the PLDs using PSD-
soft Express, the logic is programmed into the de-
vice and available upon Power-up.
The PLDs have selectable levels of performance
and power consumption.
The device contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD), as shown
in
Figure 6., page 25
.
The DPLD performs address decoding, and gen-
erates select signals for internal and external com-
ponents, such as memory, registers, and I/O ports.
The DPLD can generate eight External Chip Se-
lect (ECS0-ECS7) signals on Port C.
The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array.
The AND Array is used to form product terms.
These product terms are configured from the logic
definition entered in PSDsoft Express. A PLD In-
put Bus consisting of 73 signals is connected to
the PLDs. Input signals are shown in Table
10
.
Turbo Bit
The PLDs in the device can minimize power con-
sumption by switching to standby when inputs re-
main unchanged for an extended time t
TURBO
.
Resetting the Turbo Bit to
’
0
’
(Bit 3 of the PMMR0
register) automatically places the PLDs into stand-
by if no inputs are changing. Turning the Turbo
Mode off increases propagation delays while re-
ducing power consumption. Additionally, seven
bits are available in the PMMR registers in csiop to
block DSP control signals from entering the PLDs.
This reduces power consumption and can be used
only when these DSP control signals are not used
in PLD logic equations. Each of the two PLDs has
unique characteristics suited for its applications.
They are described in the following sections.
Table 10. DPLD and CPLD Inputs
Note: 1. DSP address lines above A15 may enter the DSM device
on any pin on ports A, B, C or D. See Appendices for rec-
ommended connections.
2. Additional DSP control signals may enter the DMS device
on any pin on Ports A, B, C, or D. See Appendices for rec-
ommended connections.
Input Source
Input Name
Number
of
Signals
DSP Address Bus
1
A15-A0
16
DSP Control Signals
2
CNTL2-CNTL0
3
Reset
RST
1
PortA Input Macrocells
PA7-PA0
8
PortB Input Macrocells PB7-PB0
8
PortC Input Macrocells PC7-PC0
8
Port D Inputs
PD3-PD0
4
Page Register
PG7-PG0
8
Macrocell A Feedback MCELLA FB7-0
8
Macrocell B Feedback MCELLB FB7-0
8
Flash memory
Program Status Bit
Ready/Busy
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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