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參數(shù)資料
| 型號： | DSM2150F5V-12T6 |
| 廠商： | 意法半導體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號處理器系統(tǒng)內(nèi)存）的ADI公司的DSP（3.3V電源） |
| 文件頁數(shù)： | 41/73頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | DSM2150F5V-12T6 |
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DSM2150F5V
I/O PORTS
There are seven programmable I/O ports: Ports A,
B, C, D, E, F, and G. However, typically only four
of these ports are available in 8-bit DSP data con-
figuration, and 3 ports with 16-bit data. Each of the
ports is eight bits except Port D, which is 4 bits.
Each port pin is individually user configurable, thus
allowing multiple functions per port. The ports are
configured using PSDsoft Express
or by the DSP
writing to on-chip registers in the csiop block.
The topics discussed in this section are:
General Port architecture
Port operating modes
csiop Port registers
Port Data Registers
Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
shown in
Figure 19., page 44
. Individual Port ar-
chitectures are shown in
Figure 19., page 44
to
Figure 21., page 46
. In general, once the purpose
for a port pin has been defined in PSDsoft Ex-
press
, that pin is no longer available for other
purposes. Exceptions are noted.
The ports contain an output multiplexer whose se-
lect signals are driven by the configuration bits de-
termined by PSDsoft Express. Inputs to the
multiplexer include the following:
Output data from the Data Out register (for
MCU I/O Mode)
CPLD Macrocell output (OMC)
External Chip Selects ESC0-7 from the DPLD
to Port C pins only.
I
I
I
I
I
I
I
I
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read by the
DSP. The Port Data Buffer (PDB) is connected to
the Internal Data Bus for feedback and can be
read by the DSP. The Data Out and Macrocell out-
puts, Direction and Drive Registers, and port pin
input are all connected to the Port Data Buffer
(PDB).
The Port pin
’
s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in PSDsoft Express
, then the Direction Register
has sole control of the buffer that drives the port
pin.
The contents of these registers can be altered by
the DSP. The Port Data Buffer (PDB) feedback
path allows the DSP to check the contents of the
registers.
Ports A, B, and C have IMCs. The IMCs can be
configured as registers (for sampling or debounc-
ing), as transparent latches, or direct inputs to the
PLDs. The registers and latches are clocked by a
product term from the PLD AND Array. The out-
puts from the IMCs drive the PLD input bus and
can
be
read
by
the
Macrocell, page 32
.
Port Operating Modes
The I/O Ports have several modes of operation.
Modes are defined using PSDsoft Express
, and
then runtime control from the DSP can occur using
the registers in the csiop block. See Application
Note
AN1171
for more detail.
Table 13., page 43
summarizes which modes are
available on each port. Each of the port operating
modes are described in the following sections.
DSP.
See
Input
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