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參數(shù)資料
| 型號(hào)： | DSM2150F5V-12T6 |
| 廠(chǎng)商： | 意法半導(dǎo)體 |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存）的ADI公司的DSP（3.3V電源） |
| 文件頁(yè)數(shù)： | 49/73頁(yè) |
| 文件大?。?/td> | 1067K |
| 代理商： | DSM2150F5V-12T6 |
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DSM2150F5V
PROGRAMMING IN-CIRCUIT USING JTAG ISP
In-System Programming (ISP) can be performed
through the JTAG signals on Port E. This serial in-
terface allows programming of the entire DSM de-
vice or subsections (i.e. only Flash memory but not
the PLDs) without and participation of the DSP. A
blank DSM device soldered to a circuit board can
be completely programmed in 15to 35 seconds.
The basic JTAG signals; TMS, TCK, TDI, and
TDO form the IEEE-1149.1 interface. The DSM
device does not implement the IEEE-1149.1
Boundary Scan functions. The DSM uses the
JTAG interface for ISP only. However, the DSM
device can reside in a standard JTAG chain with
other JTAG devices as it will remain in BYPASS
Mode while other devices perform Boundary
Scan.
ISP programming time can be reduced as much as
30% by using two more signals on Port E, TSTAT
and TERR in addition to TMS, TCK, TDI and TDO.
See Table
15
. The FlashLINK
JTAG
program-
ming cable available from STMicroelectronics for
$USD59 and PSDsoft Express software that is
available at no charge from
www.st.com/psm
is
all that is needed to program a DSM device using
the parallel port on any PC or laptop.
By default, the four pins on Port C are enabled for
the basic JTAG signals TMS, TCK, TDI, and TDO
on a blank device (and as shipped from factory).
See Application Note
AN1153
for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG signals
(TMS, TCK, TDI, and TDO) on their respective
Port E pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG operation.
When JTAG_ON is false, the four pins can be
used for general device I/O as specified in PSD-
soft Express.
JTAG_ON can become true by any of three differ-
ent ways as shown:
JTAG_ON =
1.
PSDsoft Express Pin Configuration -OR-
2.
PSDsoft Express PLD equation -OR-
3.
DSP writes to register in csiop block
Method 1.
is most common. This is when the
JTAG pins are selected in PSDsoft Express to be
“
dedicated
”
JTAG pins. They can always transmit
and receive JTAG information because they are
“
full-time
”
JTAG pins.
Method 2.
is used only when the JTAG pins are
multiplexed with general I/O functions. For de-
signs that need every I/O pin, the JTAG pins may
be used for general I/O when they are not used for
ISP. However, when JTAG pins are multiplexed
with general I/O functions, the designer must in-
clude a way to get the pins back into JTAG Mode
when it is time for JTAG operations again. In this
case, a single PLD input from Ports A, B, C, or D
must be dedicated to switch the Port E pins from I/
O Mode back to ISP Mode at any time. It is recom-
mended to physically connect this dedicated PLD
input pin to the JEN\ output signal from the
Flashlink cable when multiplexing JTAG signals.
See Application Note
AN1153
for details.
Method 3.
is rarely used to control JTAG pin op-
eration. The DSP can set the port E pins to func-
tion as JTAG ISP by setting the JTAG Enable Bit
in a register of the csiop block, but as soon as the
DSM chip is reset, the csiop block registers are
cleared, which turns off the JTAG-ISP function.
Controlling JTAG pins using this method is not rec-
ommended.
Table 15. JTAG Port Signals
Port E Pin
JTAG Signals
Description
PE0
TMS
Mode Select
PE1
TCK
Clock
PE2
TDI
Serial Data In
PE3
TDO
Serial Data Out
PE4
TSTAT
Status
PE5
TERR
Error Flag
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相關(guān)代理商/技術(shù)參數(shù) |
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| DSM2150F5V-12T6T | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:EEPROM |
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