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參數(shù)資料
| 型號(hào)： | DSM2150F5V-12T6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存）的ADI公司的DSP（3.3V電源） |
| 文件頁數(shù)： | 43/73頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | DSM2150F5V-12T6 |
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DSM2150F5V
Drive Select Register
The Drive Select Register configures the pin driver
as Open Drain or CMOS (standard push/pull) for
some port pins, and controls the slew rate for the
other port pins. An external pull-up resistor should
be used for pins configured as Open Drain. Open
Drain outputs are diode clamped, thus the maxi-
mum voltage on an pin configured as Open Drain
is V
CC
+ 0.7V.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
’
1.
’
The default pin drive is CMOS.
Note:
The slew rate is a measurement of the rise
and fall times of an output. A higher slew rate
means a faster output response and may create
more electrical noise. A pin operates in a high slew
rate when the corresponding bit in the Drive Reg-
ister is set to
’
1.
’
The default rate is standard slew.
See Appendix A for Drive Register bit definitions.
DSP Data Bus
Port F is used for DSP data lines D0-D7 when
DSM2150F5V is configured for 8-bit operation.
Port G is additionally used for DSP data lines D8-
D15 when configured for 16-bit operation.
PLD Inputs
Inputs from Ports A, B, and C to the DPLD and
CPLD come through IMCs. Inputs from Port D to
PLDs are routed directly in and do not use IMCs.
PLD Outputs
Outputs from the CPLD to Port A come from the
OMC group MCELLA0-7. Likewise, Port B is driv-
en by MCELLB0-7. Outputs from the DPLD to Port
C come from the external chip select logic block
ECS0-7.
JTAG In-System Programming (ISP)
Some of the pins on Port E implement IEEE
1194.1 JTAG bus for In-System Programming
(ISP). You can multiplex the function of these Port
E JTAG pins with other functions. See the section
entitled
“
Programming In-Circuit Using JTAG ISP
”
,
and Application Note
AN1153
.
Enable Out
The Enable Out register can be read by the DSP.
It contains the output enable values for a given
port. A logic
’
1
’
indicates the driver is in output
mode. A logic
’
0
’
indicates the driver is in tri-state
and the pin is in input mode.
Table 13. Port Operating Modes
Note: 1. Can be multiplexed with other I/O functions.
2. Only in 8-bit DSP data bus configuration.
Port Mode
Port A
Port B
Port C
Port D
Port E
Port F
Port G
MCU I/O
Yes
Yes
Yes
Yes
Yes
No
Yes
2
DSP data bus for 8-bit config
DSP data bus for 16-bit config
PLD Input though IMC
PLD Input directly
McellA Outputs
McellB Outputs
Additional External CS Outputs
No
No
Yes
No
Yes
No
No
No
No
Yes
No
No
Yes
No
No
No
Yes
No
No
No
Yes
No
No
No
Yes
No
No
No
No
No
No
No
No
No
No
Yes
Yes
No
No
No
No
No
No
Yes
No
No
No
No
No
JTAG ISP
No
No
No
No
Yes
1
No
No
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