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參數(shù)資料
| 型號： | DSM2150F5V-12T6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號處理器系統(tǒng)內(nèi)存）的ADI公司的DSP（3.3V電源） |
| 文件頁數(shù)： | 8/73頁 |
| 文件大?。?/td> | 1067K |
| 代理商： | DSM2150F5V-12T6 |
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DSM2150F5V
8/73
PIN DESCRIPTION
Table 3. Pin Description (Pin Assignments in Appendix
A
)
Pin Name
Type
Description
AD0-15
In
Sixteen address inputs from the DSP.
CNTL0
In
Active low WRITE strobe input from the DSP typically connected to DSP WR signal.
Also functions as WRL for DSPs which use WRL strobe when writing low byte only in 16-bit word.
CNTL1
In
Active low READ strobe input from the DSP
CNTL2
In
Programmable control input.
CNTL2 may be used for BHE (Byte High Enable) when DSM2150F5V is configured for 16-bit
operation. BHE =
’
0
’
will allow a byte WRITE from data lines D8-D15 ignoring data lines D0-D7.
BHE = 1 will allow a byte WRITE from D0-D7 ignoring data lines D8-D15. DSP READ operations
are not affected by BHE (always read both bytes).
Reset
In
Active low reset input from system.
Resets DSM I/O Ports, Page Register contents, and other DSM configuration registers. Must be
logic Low at Power-up.
PA0-7
I/O
Eight configurable Port A signals with the following functions:
–
MCU I/O
–
DSP may write or read pins directly at runtime with csiop registers.
–
CPLD Output Macrocell (McellA0-7) outputs.
–
Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above.
Note:
PA0-PA7 may be configured at run-time as standard CMOS or Open Drain Outputs.
PB0-7
I/O
Eight configurable Port B signals with the following functions:
–
MCU I/O
–
DSP may write or read pins directly at runtime with csiop registers.
–
CPLD Output Macrocell (McellB0-7 or McellC0-7) outputs.
–
Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above.
Note:
PB0-PB7 may be configured at run-time as standard CMOS or Open Drain Outputs.
PC0-7
I/O
Eight configurable Port C signals with the following functions:
–
MCU I/O
–
DSP may write or read pins directly at runtime with csiop registers.
–
DPLD chip-select outputs (ECS0-7, does not consume MicroCells).
–
Inputs to the PLDs (via Input Macrocells). Can be used to input address A16 and above.
Note:
PC0-PC7 may be configured at run-time as standard CMOS or Faster Slew Rate Output.
PD0-3
I/O
Four configurable Port D signals with the following functions:
–
MCU I/O
–
DSP may write or read pins directly at runtime with csiop registers.
–
Input to the PLDs (no associated Input Macrocells, routes directly into PLDs). Can be used to
input address A16 and above.
–
PD1 can be configured as CLKIN, a common clock input to PLD.
–
PD2 can be configured as CSI, active low Chip Select Input to select Flash memory. Flash
memory is disabled to conserve more power when CSI is logic high.
–
PD3 can be used for WRH strobe from DSP to write high byte only for 16-bit configuration.
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相關(guān)代理商/技術(shù)參數(shù) |
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