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參數(shù)資料
| 型號(hào)： | DSM2150F5V-12T6 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSM (Digital Signal Processor System Memory) for Analog Devices DSPs (3.3V Supply) |
| 中文描述： | 帝斯曼（數(shù)字信號(hào)處理器系統(tǒng)內(nèi)存）的ADI公司的DSP（3.3V電源） |
| 文件頁(yè)數(shù)： | 48/73頁(yè) |
| 文件大小： | 1067K |
| 代理商： | DSM2150F5V-12T6 |
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DSM2150F5V
48/73
RESET TIMING AND DEVICE STATUS AT RESET
Power On Reset
Upon Power-up, the device requires a Reset (
RE-
SET
) pulse of duration t
NLNH-PO
after V
CC
is
steady. During this time period, the device loads
internal configurations, clears some of the regis-
ters and sets the Flash memory into Read Array
Mode. After the rising edge of Reset (
RESET
), the
device remains in the Reset Mode for an additional
period, t
OPR
, before the first memory access is al-
lowed.
Upon Power On reset, internal sector selects FS0-
7 and CSBOOT0-7 must all be inactive and Write
Strobe (
WR
, CNTL0) inactive (logic
’
1
’
) for maxi-
mum security of the data contents and to remove
the possibility of a byte/word being written on the
first edge of Write Strobe (
WR
, CNTL0). Any Flash
memory WRITE cycle initiation is prevented auto-
matically when V
CC
is below V
LKO
.
Warm Reset
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
t
NLNH
. The same t
OPR
period is needed before the
device is operational after warm reset. Figure
22
shows the timing of the Power-up and warm reset.
I/O Pin, Register, and PLD Status at Reset
Table
14
shows the I/O pin, register and PLD sta-
tus during Power-on Reset, warm reset and Pow-
er-down Mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal device Configuration bits
are loaded. This loading of the device is completed
typically long before the V
CC
ramps up to operat-
ing level. Once the PLD is active, the state of the
outputs are determined by the PSDsoft Express
equations.
Figure 22. Reset (RESET) Timing
Table 14. Status During Power-on Reset, Warm Reset and Power-down Mode
Port Configuration
Power-on Reset
Warm Reset
MCU I/O
Input Mode
Input Mode
PLD Output
Valid after internal PSD configuration
bits are loaded (almost immediately)
Valid
Register
Power-on Reset
Warm Reset
PMMR0 and PMMR2
Cleared to
’
0
’
Unchanged
OMC Flip-flop status
Cleared to
’
0
’
by internal Power-on
Reset
Depends on .re and .pr equations
All other registers
Cleared to
’
0
’
Cleared to
’
0
’
tNLNH-PO
Power-On Reset
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
Warm Reset
tOPR
V
CC
V
CC
(min)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSM2150F5V-12T6T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:EEPROM |
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