參數(shù)資料
型號: EDD51321CBH
廠商: Elpida Memory, Inc.
英文描述: 512M bits DDR SDRAM
中文描述: 512M比特DDR內(nèi)存
文件頁數(shù): 21/55頁
文件大?。?/td> 589K
代理商: EDD51321CBH
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
21
Extended Mode Register
The extended mode register is as follows;
Reserved
Driver Strength
Following extended mode register programming, no command can be issued before at least 2 clocks have elapsed.
Driver Strength
By setting specific parameter on A6 and A5, driving capability of data output drivers is selected.
: A12 through A7, A4 through A0
: A6 through A5
Power-Down Mode and CKE Control
DDR SDRAM will be into power-down mode at the second CK rising edge after CKE to be low level with NOP or
DESL command at first CK rising edge after CKE signal to be low.
CK
/CK
CKE
Address
Power-down mode
Command
NOP
Valid*
2
NOP
NOP
Valid*
1
Valid*
2
Valid*
1
Notes: 1. Valid*
1
can be either Activate command or Precharge command, When Valid*
1
is Activate command,
power-down mode will be active power-down mode, while it will be precharge power down mode,
if Valid*
1
will be Precharge command.
2. Valid*
2
can be any command as long as all of specified AC parameters are satisfied.
Power-Down Entry and Exit
However, if the CKE has one clock cycle high and on clock cycle low just as below, even DDR SDRAM will not enter
power-down mode, this command flow does not hurt any data and can be done.
CK
/CK
CKE
Command
ACT
NOP
NOP
PRE
Note: Assume PRE and ACT command is closing and activating same bank.
CKE Control
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相關(guān)代理商/技術(shù)參數(shù)
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