參數(shù)資料
型號: EDD51321CBH
廠商: Elpida Memory, Inc.
英文描述: 512M bits DDR SDRAM
中文描述: 512M比特DDR內(nèi)存
文件頁數(shù): 25/55頁
文件大小: 589K
代理商: EDD51321CBH
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
25
CK
/CK
VTT
VTT
DQS
DQ
Command
t0
t0.5
t1
t1.5
t2
t2.5
t3
t3.5
t4
t4.5
t5
t5.5
out0
out1
out2
out3
tAC,tDQSCK
READ
NOP
tRPRE
tRPST
Read Operation (/CAS Latency)
Write operation
The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued.
The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4
or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by
the column address, the bank select address (See “Pin Function”) in the cycle when the write command is issued.
DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first
rising edge of DQS, DQS must be set to low. tWPST after the last falling edge of DQS, the DQS pins can be
changed to high-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is
referred as write postamble.
in1
in0
in1
in2
in3
in0
in1
in2
in3
in4
in5
in6
in7
CK
/CK
Address
DQS
DQ
BL = 2
BL = 4
BL = 8
Command
BL: Burst length
in0
ACT
NOP
NOP
NOP
WRIT
tWPRE
tWPRES
Row
Column
tRCD
tWPST
Write Operation
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