參數(shù)資料
型號(hào)： EDD51321CBH
廠商： Elpida Memory, Inc.
英文描述： 512M bits DDR SDRAM
中文描述： 512M比特DDR內(nèi)存
文件頁(yè)數(shù)： 38/55頁(yè)
文件大?。?/td> 589K
代理商： EDD51321CBH
EDD51321CBH
Preliminary Data Sheet E1094E30 (Ver. 3.0)
38
A Read command to the consecutive Precharge command interval
Operation by each case of destination bank of the consecutive Precharge command.
Bank address
Operation
1.
Same
The PRE and PALL command can interrupt a read operation.
To complete a burst read operation, tRPD is required between the read and the precharge
command. Please refer to the following timing chart.
The PRE command does not interrupt a read command.
No interval timing is required between the read and the precharge command.
2.
Different
READ to PRECHARGE Command Interval (same bank) : To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
CK
/CK
DQ
DQS
Command
t1
t0
t2
t3
t4
t5
t6
t7
t8
tRPD = BL/2
NOP
NOP
NOP
PRE/
PALL
out0 out1 out2 out3
READ
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become high-Z tHZP
(= CL) after the precharge command.
out0
CK
/CK
DQ
DQS
Command
t1
t0
t2
t3
t4
t5
t6
t7
t8
High-Z
High-Z
tHZP
READ
NOP
NOP
PRE/PALL
out1
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 4, 8)
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