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參數(shù)資料
| 型號： | Embedded Pentium Processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式電壓還原技術(shù)奔騰處理器（32位嵌入式帶壓降技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 18/44頁 |
| 文件大?。?/td> | 826K |
| 代理商： | EMBEDDED PENTIUM PROCESSOR |
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Embedded Pentium
Processor with Voltage Reduction Technology
18
Datasheet
BUSCHK#
I
The
bus check
input allows the system to signal an unsuccessful completion of a
bus cycle. If this pin is sampled active, the processor will latch the address and
control signals in the machine check registers. If, in addition, the MCE bit in CR4 is
set, the processor will vector to the machine check exception.
CACHE#
O
For processor-initiated cycles, the
cache
pin indicates internal cacheability of the
cycle (if a read), and indicates a burst writeback cycle (if a write). If this pin is driven
inactive during a read cycle, the processor does not cache the returned data,
regardless of the state of the KEN# pin. This pin is also used to determine the cycle
length (number of transfers in the cycle).
CLK
I
The
clock
input provides the fundamental timing for the processor. Its frequency is
the operating frequency of the processor’s external bus and requires TTL levels. All
external timing parameters except TDI, TDO, TMS, and TRST# are specified with
respect to the rising edge of CLK.
It is recommended that CLK begin 150 ms after V
CC
reaches its proper operating
level. This recommendation is only to assure the long term reliability of the device.
D/C#
O
The
data/code
output is one of the primary bus cycle definition pins. It is driven
valid in the same clock in which the ADS# signal is asserted. D/C# distinguishes
between data and code or special cycles.
D63–D0
I/O
These are the 64
data lines
for the processor. Lines D7–D0 define the least
significant byte of the data bus; lines D63–D56 define the most significant byte of
the data bus. When the processor is driving the data lines, they are driven during
the T2, T12 or T2P clocks for that cycle. During reads, the processor samples the
data bus when BRDY# is returned.
DP7–DP0
I/O
These are the
data parity
pins for the processor. There is one for each byte of the
data bus. They are driven by the processor with even parity information on writes in
the same clock as write data. Even parity information must be driven back to the
embedded Pentium processor with voltage reduction technology on these pins in
the same clock as the data to ensure that the correct parity check status is indicated
by the processor. DP7 applies to D63–D56; DP0 applies to D7–D0.
EADS#
I
This signal indicates that a valid
external address
has been driven onto the
processor address pins to be used for an inquire cycle.
EWBE#
I
The
external write buffer empty
input, when inactive (high), indicates that a write
cycle is pending in the external system. When the processor generates a write and
EWBE# is sampled inactive, the processor will hold off all subsequent writes to all
E- or M-state lines in the data cache until all write cycles have completed, as
indicated by EWBE# being active.
FERR#
O
The
floating-point error
pin is driven active when an unmasked floating-point error
occurs. FERR# is similar to the ERROR# pin on the Intel387 math coprocessor.
FERR# is included for compatibility with systems using DOS-type floating-point
error reporting.
FLUSH#
I
When asserted, the
cache flush
input forces the processor to write back all
modified lines in the data cache and invalidate its internal caches. A Flush
Acknowledge special cycle is generated by the processor indicating completion of
the writeback and invalidation.
If FLUSH# is sampled low when RESET transitions from high to low, three-state test
mode is entered.
HIT#
O
The
hit
indication is driven to reflect the outcome of an inquire cycle. If an inquire
cycle hits a valid line in either the data or instruction cache, this pin is asserted two
clocks after EADS# is sampled asserted. If the inquire cycle misses the cache, this
pin is negated two clocks after EADS#. This pin changes its value only as a result of
an inquire cycle and retains its value between the cycles.
Table 5. Pin Quick Reference
Symbol
Type
Function
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