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參數(shù)資料
| 型號： | Embedded Pentium Processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式電壓還原技術(shù)奔騰處理器（32位嵌入式帶壓降技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 8/44頁 |
| 文件大?。?/td> | 826K |
| 代理商： | EMBEDDED PENTIUM PROCESSOR |
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Embedded Pentium
Processor with Voltage Reduction Technology
8
Datasheet
Address parity
Internal parity checking
Execution tracing
Performance monitoring
IEEE 1149.1 boundary scan
System Management Mode
Virtual Mode extensions
Voltage reduction technology
SL Power management features
2.1
Pentium
Processor Family Architecture
The application instruction set of the Pentium processor family includes the complete Intel486
processor family instruction set with extensions to accommodate some of the additional
functionality of the Pentium processor. All application software written for the Intel386 and
Intel486 family microprocessors runs on Pentium processors without modification. The on-chip
memory management unit is completely compatible with the Intel386 family and Intel486 family
of processors.
Pentium processors implement several enhancements to increase performance. The two instruction
pipelines and the floating-point unit are capable of independent operation. Each pipeline issues
frequently used instructions in a single clock. Together, the dual pipes can issue two integer
instructions in one clock, or one floating-point instruction (under certain circumstances, two
floating-point instructions) in one clock.
Branch prediction is implemented in Pentium processors. To support this, the processor has two
prefetch buffers, one to prefetch code in a linear fashion, and one that prefetches code according to
the BTB so the needed code is almost always prefetched before it is needed for execution.
The floating-point unit (FPU) is up to ten times faster than the FPU used on the Intel486 processor
for common operations including add, multiply, and load.
Pentium processors include separate code and data caches integrated on-chip to meet performance
goals. Each cache is 8 Kbytes with a 32-byte line size, and is two-way set associative. Each cache
has a dedicated Translation Lookaside Buffer (TLB) to translate linear addresses to physical
addresses. The data cache is configurable to be write back or write through on a line-by-line basis
and follows the MESI protocol. The data cache tags are triple-ported to support two data transfers
and an inquire cycle in the same clock. The code cache is an inherently write-protected cache. The
code cache tags are also triple-ported to support snooping and split-line accesses. Individual pages
can be configured as cacheable or non-cacheable by software or hardware. The cache can be
enabled or disabled by software or hardware.
Pentium processors have a 64-bit data bus for fast data transfer. Burst read and burst writeback
cycles are supported. In addition, bus cycle pipelining has been added to allow two bus cycles to
occur simultaneously. The Memory Management Unit contains optional extensions to the
architecture which allow 2-Mbyte and 4-Mbyte page sizes.
Pentium processors have added significant data integrity and error detection capability. Data parity
checking is still supported on a byte-by-byte basis. Address parity checking and internal parity
checking features have been added along with a new exception, the machine check exception.
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