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參數(shù)資料
| 型號： | Embedded Pentium Processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式電壓還原技術(shù)奔騰處理器（32位嵌入式帶壓降技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 19/44頁 |
| 文件大?。?/td> | 826K |
| 代理商： | EMBEDDED PENTIUM PROCESSOR |
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Embedded Pentium
Processor with Voltage Reduction Technology
Datasheet
19
O
The
hit to a modified line
output is driven to reflect the outcome of an inquire cycle.
It is asserted after an inquire cycle that results in a hit to a modified line in the data
cache. It is used to inhibit another bus master from accessing the data until the line
is completely written back.
HLDA
O
The
bus hold acknowledge
pin goes active in response to a hold request driven to
the processor on the HOLD pin. It indicates that the processor has floated most of
the output pins and relinquished the bus to another local bus master. When leaving
bus hold, HLDA is driven inactive and the processor resumes driving the bus. If the
processor has a bus cycle pending, it will be driven in the same clock in which HLDA
is deasserted.
HOLD
I
In response to the
bus hold request
, the processor will float most of its output and
input/output pins and assert HLDA after completing all outstanding bus cycles. The
processor will maintain its bus in this state until HOLD is deasserted. HOLD is not
recognized during LOCK cycles. The processor will recognize HOLD during reset.
IERR#
O
The
internal error
pin is used to indicate internal parity errors. If a parity error
occurs on a read from an internal array, the processor will assert the IERR# pin for
one clock and then shutdown.
IGNNE#
I
The
ignore numeric error
input has no effect when the NE bit in CR0 is set to 1.
When the CR0.NE bit is 0 and the IGNNE# pin is asserted, the processor ignores
any pending unmasked numeric exception and continues executing floating-point
instructions for the entire duration that this pin is asserted. When the CR0.NE bit is
0, IGNNE# is not asserted, a pending unmasked numeric exception exists (SW.ES
= 1), and the floating-point instruction is one of FINIT, FCLEX, FSTENV, FSAVE,
FSTSW, FSTCW, FENI, FDISI, or FSETPM, the processor will execute the
instruction in spite of the pending exception. When the CR0.NE bit is 0, IGNNE# is
not asserted, a pending unmasked numeric exception exists (SW.ES = 1), and the
floating-point instruction is one other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW,
FSTCW, FENI, FDISI, or FSETPM, the processor will stop execution and wait for an
external interrupt.
INIT
I
The processor
initialization
input pin forces the processor to begin execution in a
known state. The processor state after INIT is the same as the state after RESET
except that the internal caches, write buffers, and floating-point registers retain the
values they had prior to INIT. INIT may NOT be used in lieu of RESET after power
up.
If INIT is sampled high when RESET transitions from high to low, the processor will
perform built-in self test prior to the start of program execution.
INTR
I
An active
maskable interrupt
input indicates that an external interrupt has been
generated. If the IF bit in the EFLAGS register is set, the processor will generate two
locked interrupt acknowledge bus cycles and vector to an interrupt handler after the
current instruction execution is completed. INTR must remain active until the first
interrupt acknowledge cycle is generated to ensure that the interrupt is recognized.
INV
I
The
invalidation
input determines the final cache line state (S or I) in case of an
inquire cycle hit. It is sampled together with the address for the inquire cycle in the
clock in which EADS# is sampled active.
KEN#
The
cache enable
pin is used to determine whether the current cycle is cacheable
or not and is consequently used to determine cycle length. When the processor
generates a cycle that can be cached (CACHE# asserted) and KEN# is active, the
cycle will be transformed into a burst line fill cycle.
LOCK#
O
The
bus lock
pin indicates that the current bus cycle is locked. The processor does
not allow a bus hold when LOCK# is asserted (but AHOLD and BOFF# are
allowed). LOCK# goes active in the first clock of the first locked bus cycle and goes
inactive after the BRDY# is returned for the last locked bus cycle. LOCK# is
guaranteed to be deasserted for at least one clock between back-to-back locked
cycles.
Table 5. Pin Quick Reference
Symbol
Type
Function
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