參數(shù)資料
型號(hào)： Embedded Pentium Processor
廠商： Intel Corp.
英文描述： 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術(shù)奔騰處理器)
中文描述： 32位嵌入式電壓還原技術(shù)奔騰處理器（32位嵌入式帶壓降技術(shù)奔騰處理器）
文件頁(yè)數(shù)： 31/44頁(yè)
文件大?。?/td> 826K
代理商： EMBEDDED PENTIUM PROCESSOR
Embedded Pentium
Processor with Voltage Reduction Technology
Datasheet
31
These capacitors should be placed near the processor (on the 3.3-V plane and the 3.1-V plane or
island) to ensure that these supply voltages stay within specified limits during changes in the power
demands of the processor during operation.
For more detailed information, please contact Intel or refer to the
Pentium
Processor with Voltage
Reduction Technology: Power Supply Design Considerations for Mobile Systems
application note
(order number 242558).
Note:
Capacitors degrade over time during use. As capacitors age, their capacity to store and hold a
charge becomes compromised. Designing a board with below minimum acceptable bypass and
bulk capacitors may have future system reliability consequences.
4.3.3
Connection Specifications
All NC pins must remain unconnected. Refer to Table 4 for a list of NC pins.
For reliable operation, always connect unused inputs to an appropriate signal level. Unused active
low inputs should be connected to V
CC3
. Unused active high inputs should be connected to ground.
4.3.4
AC Timings
The AC specifications given in Table 17 consist of output delays, input setup requirements and
input hold requirements for the 66-MHz external bus. All AC specifications (with the exception of
those for the TAP signals and APIC signals) are relative to the rising edge of the CLK input.
All timings are referenced to 1.5 V for both 0 and 1 logic levels unless otherwise specified. Within
the sampling window, a synchronous input must be stable for correct operation.
Table 17. AC Specifications (Sheet 1 of 4)
V
CC2
= 3.1 V ±165 mV; V
CC3
= 3.3 V ±165 mV; T
CASE
= 0
°
C to 85
°
C; CL = 0 pF
Symbol
Parameter
Min
Max
Unit
Figure
Notes
Frequency
33.33
66.6
MHz
t
1a
t
1b
t
2
t
3
t
4
t
5
CLK Period
15.0
30.0
ns
6
CLK Period Stability
±
250
ps
1, 19
CLK High Time
4.0
ns
6
@2 V, Note 1
CLK Low Time
4.0
ns
6
@0.8 V, Note 1
CLK Fall Time
0.15
1.5
ns
6
2.0 V–0.8 V, Note 1
CLK Rise Time
0.15
1.5
ns
6
0.8 V–2.0 V, Note 1
t
6a
PWT, PCD, BE7#–BE0#, D/C#,
W/R#, CACHE#, SCYC Valid
Delay
1.0
7.0
ns
7
t
6b
t
6c
t
6d
t
6e
t
6f
AP Valid Delay
1.0
8.5
ns
7
LOCK# Valid Delay
1.1
7.0
ns
7
ADS# Valid Delay
1.0
6.0
ns
7
A31–A3 Valid Delay
1.1
6.3
ns
7
M/IO# Valid Delay
1.0
5.9
ns
7
NOTE:
See Table 18 for table notes.
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