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參數(shù)資料
| 型號： | Embedded Pentium Processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式電壓還原技術(shù)奔騰處理器（32位嵌入式帶壓降技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 28/44頁 |
| 文件大小： | 826K |
| 代理商： | EMBEDDED PENTIUM PROCESSOR |
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Embedded Pentium
Processor with Voltage Reduction Technology
28
Datasheet
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
The following values are stress ratings only. Functional operation at the maximum ratings is not
implied nor guaranteed. Functional operating conditions are given in the AC and DC specification
tables.
Extended operation beyond the maximum ratings may affect device reliability. Furthermore,
although the embedded Pentium processor with voltage reduction technology contains protective
circuitry to resist damage from static electric discharge, always take precautions to avoid high
static voltages or electric fields.
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only.
4.2
DC Specifications
Tables 14, 15 and 16 list the DC specifications that apply to the embedded Pentium processor with
voltage reduction technology. The embedded Pentium processor with voltage reduction technology
core operates at 3.1 V internally while the I/O interface operates at 3.3 V. The CLK input may be at
3.3 V or 5 V. Since the 3.3-V (5-V safe) input levels defined in Table 15
are the same as the 5-V
TTL levels, the CLK input is compatible with existing 5V clock drivers.
Table 13. Absolute Maximum Ratings
Parameter
Maximum Rating
Case temperature under bias
65
°
C to 110
°
C
Storage temperature
65
°
C to 150
°
C
3 V Supply voltage with respect to V
SS
0.5 V to +4.6 V
3.1 V Supply voltage with respect to V
SS
0.5 V to +4.1 V
3 V Only Buffer DC Input Voltage
0.5 V to V
CC3
+0.5; not to exceed 4.6 V
1
0.5 V to 6.5 V
2, 3
5 V Safe Buffer DC Input Voltage
NOTES:
1. Applies to all SPGA embedded Pentium
processor with voltage reduction technology inputs except CLK.
2. Applies to CLK.
3. See Table 15.
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