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參數(shù)資料
| 型號： | Embedded Pentium Processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術(shù)奔騰處理器) |
| 中文描述： | 32位嵌入式電壓還原技術(shù)奔騰處理器（32位嵌入式帶壓降技術(shù)奔騰處理器） |
| 文件頁數(shù)： | 44/44頁 |
| 文件大?。?/td> | 826K |
| 代理商： | EMBEDDED PENTIUM PROCESSOR |
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Embedded Pentium
Processor with Voltage Reduction Technology
44
Datasheet
4.4.2.2
Settling Time
The settling time is defined as the time required at the receiver for the signal to settle to within 10
percent of V
CC3
or V
SS
. Settling time is also the maximum time allowed for a signal to reach
within 10 percent of its final value.
Most available simulation tools are unable to simulate settling time so that it accurately reflects
silicon measurements. On a physical board, second-order effects and other effects can dampen the
signal at the receiver. Because of all these concerns, settling time is a recommendation or a tool for
layout tuning and not a specification.
Settling time is simulated at the slow corner, to make sure that there is no impact on the flight times
of the signals if the waveform has not settled. Settling time may be simulated with the diodes
included or excluded from the input buffer model. If diodes are included, the settling time
recommendation will be easier to meet.
Although simulated settling time has not shown good correlation with physical, measured settling
time, settling time simulations can still be used as a tool to tune layouts.
Use the following procedure to verify board simulation and tuning with concerns for settling time.
1. Simulate settling time at the slow corner for a particular signal.
2. If settling time violations occur, simulate signal trace with DC diodes in place at the receiver
pin. The DC diode behaves almost identically to the actual (non-linear) diode on the part as
long as excessive overshoot does not occur.
3. If settling time violations still occur, simulate flight times for five consecutive cycles for that
particular signal.
4. If flight time values are consistent over the five simulations, settling time should not be a
concern. If however, flight times are not consistent over the five simulations, tuning of the
layout is required.
5. Note that, for signals that are allocated two cycles for flight time, the recommended settling
time is doubled.
A typical design method would include a settling time that ensures that a signal is within 10 percent
of V
CC3
or V
SS
for at least 2.5 ns prior to the end of the CLK period.
Figure 17. Settling Time
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