參數(shù)資料
型號(hào)： Embedded Pentium Processor
廠商： Intel Corp.
英文描述： 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術(shù)奔騰處理器)
中文描述： 32位嵌入式電壓還原技術(shù)奔騰處理器（32位嵌入式帶壓降技術(shù)奔騰處理器）
文件頁(yè)數(shù)： 34/44頁(yè)
文件大?。?/td> 826K
代理商： EMBEDDED PENTIUM PROCESSOR
Embedded Pentium
Processor with Voltage Reduction Technology
34
Datasheet
t
50
TRST# Pulse Width
40.0
ns
12
Asynchronous,
Note 1
t
51
t
52
t
53
t
54
t
55
t
56
t
57
t
58
TDI, TMS Setup Time
5.0
ns
11
7
TDI, TMS Hold Time
13.0
ns
11
7
TDO Valid Delay
2.8
20.0
ns
11
8
TDO Float Delay
25.0
ns
11
1, 8
All Non-Test Outputs Valid Delay
2.5
20.0
ns
11
3, 8, 10
All Non-Test Outputs Float Delay
25.0
ns
11
1, 3, 8, 10
All Non-Test Inputs Setup Time
5.0
ns
11
3, 7, 10
All Non-Test Inputs Hold Time
13.0
ns
11
3, 7, 10
Table 18. Notes for Table 17
NOTES:
Notes 2, 6 and 14 are general and apply to all standard TTL signals used with the Pentium
processor family.
1. Not 100 percent tested. Guaranteed by design.
2. TTL input test waveforms are assumed to be 0 to 3-V transitions with 1 V/ns rise and fall times.
3. Non-test outputs and inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to boundary scan operations.
4. APCHK#, FERR#, HLDA, IERR#, LOCK#, and PCHK# are glitch-free outputs. Glitch-free signals
monotonically transition without false transitions.
5. 0.8 V/ns
≤
CLK input rise/fall time
≤
8 V/ns.
6. 0.3 V/ns
≤
input rise/fall time
≤
5 V/ns.
7. Referenced to TCK rising edge.
8. Referenced to TCK falling edge.
9. 1 ns can be added to the maximum TCK rise and fall times for every 10 MHz of frequency below 33 MHz.
10. During probe mode operation, do not use the boundary scan timings (t
55–58
).
11. Setup time is required to guarantee recognition on a specific clock.
12. Hold time is required to guarantee recognition on a specific clock.
13. All TTL timings are referenced from 1.5 V.
14. To guarantee proper asynchronous recognition, the signal must have been deasserted (inactive) for a
minimum of two clocks before being returned active and must meet the minimum pulse width.
15. This input may be driven asynchronously.
16. When driven asynchronously, RESET, NMI, FLUSH#, R/S#, INIT, and SMI# must be deasserted
(inactive) for a minimum of two clocks before being returned active.
17.
The D/C#, M/IO#, W/R#, CACHE#, and A31–A5 signals are sampled only on the CLK in which ADS# is
active.
18. BF should be strapped to V
CC3
or left floating.
19. These signals are measured on the rising edge of adjacent CLKs at 1.5 V. To ensure a 1:1 relationship
between the amplitude of the input jitter and the internal and external clocks, the jitter frequency spectrum
should not have any power spectrum peaking between 500 KHz and 1/3 of the CLK operating frequency.
The amount of jitter present must be accounted for as a component of CLK skew between devices.
20. Timing (t
14
) is required for external snooping (e.g., address setup to the CLK in which EADS# is sampled
active).
21. BUSCHK# is used as a reset configuration signal to select buffer size.
22. Each valid delay is specified for a 0 pF load. The system designer should use I/O buffer modeling to
account for signal flight time delays.
Table 17. AC Specifications (Sheet 4 of 4)
V
CC2
= 3.1 V ±165 mV; V
CC3
= 3.3 V ±165 mV; T
CASE
= 0
°
C to 85
°
C; CL = 0 pF
Symbol
Parameter
Min
Max
Unit
Figure
Notes
NOTE:
See Table 18 for table notes.
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