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參數資料
| 型號： | Embedded Pentium Processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 Bit Embedded Pentium Processor with Voltage Reduction Technology(32位嵌入式帶壓降技術奔騰處理器) |
| 中文描述： | 32位嵌入式電壓還原技術奔騰處理器（32位嵌入式帶壓降技術奔騰處理器） |
| 文件頁數： | 21/44頁 |
| 文件大?。?/td> | 826K |
| 代理商： | EMBEDDED PENTIUM PROCESSOR |
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Embedded Pentium
Processor with Voltage Reduction Technology
Datasheet
21
STPCLK#
I
Assertion of the
stop clock
input signifies a request to stop the internal clock of the
embedded Pentium processor with voltage reduction technology thereby causing
the core to consume less power. When the processor recognizes STPCLK#, the
processor will stop execution on the next instruction boundary, unless superseded
by a higher priority interrupt, and generate a Stop Grant Acknowledge cycle. When
STPCLK# is asserted, the processor will still respond to external snoop requests.
TCK
I
The
testability clock
input provides the clocking function for the processor
boundary scan in accordance with the IEEE Boundary Scan interface (Standard
1149.1). It is used to clock state information and data into and out of the processor
during boundary scan.
TDI
I
The
test data input
is a serial input for the test logic. TAP instructions and data are
shifted into the processor on the TDI pin on the rising edge of TCK when the TAP
controller is in an appropriate state.
TDO
O
The
test data output
is a serial output of the test logic. TAP instructions and data
are shifted out of the processor on the TDO pin on TCK’s falling edge when the TAP
controller is in an appropriate state.
TMS
I
The value of the
test mode select
input signal sampled at the rising edge of TCK
controls the sequence of TAP controller state changes.
TRST#
I
When asserted, the
test reset
input allows the TAP controller to be asynchronously
initialized.
VCC2
I
These pins are the
3.1 V power inputs
to the embedded Pentium processor with
voltage reduction technology.
VCC3
I
These pins are the
3.3 V power inputs
to the embedded Pentium processor with
voltage reduction technology.
VSS
I
These pins are the
ground
inputs
to the embedded Pentium processor with voltage
reduction technology.
W/R#
O
Write/read
is one of the primary bus cycle definition pins. It is driven valid in the
same clock as the ADS# signal is asserted. W/R# distinguishes between write and
read cycles.
WB/WT#
I
The
writeback/writethrough
input allows a data cache line to be defined as
writeback or writethrough on a line-by-line basis. As a result, it determines whether
a cache line is initially in the S or E state in the data cache.
Table 5. Pin Quick Reference
Symbol
Type
Function
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